Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	645180065	514320118	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	645180065	3278560	0	0
GntImpliesValid_A	645180065	3278560	0	0
GrantKnown_A	645180065	514320118	0	0
IdxKnown_A	645180065	514320118	0	0
IndexIsCorrect_A	645180065	3278560	0	0
LockArbDecision_A	645180065	0	0	0
NoReadyValidNoGrant_A	645180065	0	0	0
ReadyAndValidImplyGrant_A	645180065	3278560	0	0
ReqAndReadyImplyGrant_A	645180065	3278560	0	0
ReqImpliesValid_A	645180065	3278560	0	0
ReqStaysHighUntilGranted0_M	645180065	0	0	0
RoundRobin_A	645180065	4	0	906
ValidKnown_A	645180065	514320118	0	0
gen_data_port_assertion.DataFlow_A	645180065	3278560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	514320118	0	0
T1	1838	1755	0	0
T2	915660	915344	0	0
T3	8189	7005	0	0
T4	437523	326526	0	0
T5	1015437	649724	0	0
T6	735538	451786	0	0
T7	322330	254467	0	0
T8	1016516	635565	0	0
T9	660382	560656	0	0
T10	12876	9519	0	0
T11	6678	3232	0	0
T12	48544	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0
T22	0	85448	0	0
T23	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	514320118	0	0
T1	1838	1755	0	0
T2	915660	915344	0	0
T3	8189	7005	0	0
T4	437523	326526	0	0
T5	1015437	649724	0	0
T6	735538	451786	0	0
T7	322330	254467	0	0
T8	1016516	635565	0	0
T9	660382	560656	0	0
T10	12876	9519	0	0
T11	6678	3232	0	0
T12	48544	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0
T22	0	85448	0	0
T23	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	514320118	0	0
T1	1838	1755	0	0
T2	915660	915344	0	0
T3	8189	7005	0	0
T4	437523	326526	0	0
T5	1015437	649724	0	0
T6	735538	451786	0	0
T7	322330	254467	0	0
T8	1016516	635565	0	0
T9	660382	560656	0	0
T10	12876	9519	0	0
T11	6678	3232	0	0
T12	48544	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0
T22	0	85448	0	0
T23	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	4	0	906
T21	200672	0	0	1
T24	169035	0	0	1
T28	0	1	0	0
T33	143059	0	0	1
T34	1630	0	0	1
T35	15840	0	0	1
T36	6950	0	0	1
T54	239704	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	739655	0	0	1
T58	144038	0	0	1
T59	146555	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	514320118	0	0
T1	1838	1755	0	0
T2	915660	915344	0	0
T3	8189	7005	0	0
T4	437523	326526	0	0
T5	1015437	649724	0	0
T6	735538	451786	0	0
T7	322330	254467	0	0
T8	1016516	635565	0	0
T9	660382	560656	0	0
T10	12876	9519	0	0
T11	6678	3232	0	0
T12	48544	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0
T22	0	85448	0	0
T23	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645180065	3278560	0	0
T2	687739	832	0	0
T3	7061	112	0	0
T4	328909	5241	0	0
T5	1015437	8602	0	0
T6	735538	6046	0	0
T7	322330	3219	0	0
T8	1016516	12758	0	0
T9	660382	0	0	0
T10	12876	240	0	0
T11	12266	169	0	0
T12	97088	832	0	0
T15	116924	0	0	0
T17	0	12776	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T42	0	3220	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0
T53	0	3146	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129483421	27397226	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129483421	614143	0	0
GntImpliesValid_A	129483421	614143	0	0
GrantKnown_A	129483421	27397226	0	0
IdxKnown_A	129483421	27397226	0	0
IndexIsCorrect_A	129483421	614143	0	0
LockArbDecision_A	129483421	0	0	0
NoReadyValidNoGrant_A	129483421	0	0	0
ReadyAndValidImplyGrant_A	129483421	614143	0	0
ReqAndReadyImplyGrant_A	129483421	614143	0	0
ReqImpliesValid_A	129483421	614143	0	0
ReqStaysHighUntilGranted0_M	129483421	0	0	0
RoundRobin_A	129483421	0	0	0
ValidKnown_A	129483421	27397226	0	0
gen_data_port_assertion.DataFlow_A	129483421	614143	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	27397226	0	0
T3	1128	1128	0	0
T4	108614	106312	0	0
T5	362974	62680	0	0
T6	282487	0	0	0
T7	63891	59984	0	0
T8	375408	35328	0	0
T9	93106	86584	0	0
T10	2946	2600	0	0
T11	3339	3232	0	0
T12	48544	0	0	0
T22	0	85448	0	0
T23	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	27397226	0	0
T3	1128	1128	0	0
T4	108614	106312	0	0
T5	362974	62680	0	0
T6	282487	0	0	0
T7	63891	59984	0	0
T8	375408	35328	0	0
T9	93106	86584	0	0
T10	2946	2600	0	0
T11	3339	3232	0	0
T12	48544	0	0	0
T22	0	85448	0	0
T23	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	27397226	0	0
T3	1128	1128	0	0
T4	108614	106312	0	0
T5	362974	62680	0	0
T6	282487	0	0	0
T7	63891	59984	0	0
T8	375408	35328	0	0
T9	93106	86584	0	0
T10	2946	2600	0	0
T11	3339	3232	0	0
T12	48544	0	0	0
T22	0	85448	0	0
T23	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	27397226	0	0
T3	1128	1128	0	0
T4	108614	106312	0	0
T5	362974	62680	0	0
T6	282487	0	0	0
T7	63891	59984	0	0
T8	375408	35328	0	0
T9	93106	86584	0	0
T10	2946	2600	0	0
T11	3339	3232	0	0
T12	48544	0	0	0
T22	0	85448	0	0
T23	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	614143	0	0
T3	1128	87	0	0
T4	108614	3511	0	0
T5	362974	3008	0	0
T6	282487	0	0	0
T7	63891	2116	0	0
T8	375408	1666	0	0
T9	93106	0	0	0
T10	2946	173	0	0
T11	3339	90	0	0
T12	48544	0	0	0
T17	0	4859	0	0
T42	0	3220	0	0
T53	0	3146	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129483421	100792689	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129483421	676258	0	0
GntImpliesValid_A	129483421	676258	0	0
GrantKnown_A	129483421	100792689	0	0
IdxKnown_A	129483421	100792689	0	0
IndexIsCorrect_A	129483421	676258	0	0
LockArbDecision_A	129483421	0	0	0
NoReadyValidNoGrant_A	129483421	0	0	0
ReadyAndValidImplyGrant_A	129483421	676258	0	0
ReqAndReadyImplyGrant_A	129483421	676258	0	0
ReqImpliesValid_A	129483421	676258	0	0
ReqStaysHighUntilGranted0_M	129483421	0	0	0
RoundRobin_A	129483421	0	0	0
ValidKnown_A	129483421	100792689	0	0
gen_data_port_assertion.DataFlow_A	129483421	676258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	100792689	0	0
T2	227921	227696	0	0
T3	1128	0	0	0
T4	108614	0	0	0
T5	362974	297561	0	0
T6	282487	281232	0	0
T7	63891	0	0	0
T8	375408	334546	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	0	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	100792689	0	0
T2	227921	227696	0	0
T3	1128	0	0	0
T4	108614	0	0	0
T5	362974	297561	0	0
T6	282487	281232	0	0
T7	63891	0	0	0
T8	375408	334546	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	0	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	100792689	0	0
T2	227921	227696	0	0
T3	1128	0	0	0
T4	108614	0	0	0
T5	362974	297561	0	0
T6	282487	281232	0	0
T7	63891	0	0	0
T8	375408	334546	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	0	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	100792689	0	0
T2	227921	227696	0	0
T3	1128	0	0	0
T4	108614	0	0	0
T5	362974	297561	0	0
T6	282487	281232	0	0
T7	63891	0	0	0
T8	375408	334546	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	0	48544	0	0
T15	0	116544	0	0
T17	0	114381	0	0
T18	0	2064	0	0
T19	0	29688	0	0
T20	0	189464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129483421	676258	0	0
T5	362974	6	0	0
T6	282487	1690	0	0
T7	63891	0	0	0
T8	375408	3126	0	0
T9	93106	0	0	0
T10	2946	0	0	0
T11	3339	0	0	0
T12	48544	0	0	0
T15	116924	0	0	0
T17	0	7917	0	0
T20	0	1830	0	0
T22	90065	0	0	0
T43	0	3198	0	0
T45	0	129	0	0
T47	0	7300	0	0
T48	0	4	0	0
T50	0	1056	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386213223	386130203	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	386213223	1988159	0	0
GntImpliesValid_A	386213223	1988159	0	0
GrantKnown_A	386213223	386130203	0	0
IdxKnown_A	386213223	386130203	0	0
IndexIsCorrect_A	386213223	1988159	0	0
LockArbDecision_A	386213223	0	0	0
NoReadyValidNoGrant_A	386213223	0	0	0
ReadyAndValidImplyGrant_A	386213223	1988159	0	0
ReqAndReadyImplyGrant_A	386213223	1988159	0	0
ReqImpliesValid_A	386213223	1988159	0	0
ReqStaysHighUntilGranted0_M	386213223	0	0	0
RoundRobin_A	386213223	4	0	906
ValidKnown_A	386213223	386130203	0	0
gen_data_port_assertion.DataFlow_A	386213223	1988159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	386130203	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	386130203	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	386130203	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	4	0	906
T21	200672	0	0	1
T24	169035	0	0	1
T28	0	1	0	0
T33	143059	0	0	1
T34	1630	0	0	1
T35	15840	0	0	1
T36	6950	0	0	1
T54	239704	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	739655	0	0	1
T58	144038	0	0	1
T59	146555	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	386130203	0	0
T1	1838	1755	0	0
T2	687739	687648	0	0
T3	5933	5877	0	0
T4	220295	220214	0	0
T5	289489	289483	0	0
T6	170564	170554	0	0
T7	194548	194483	0	0
T8	265700	265691	0	0
T9	474170	474072	0	0
T10	6984	6919	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386213223	1988159	0	0
T2	687739	832	0	0
T3	5933	25	0	0
T4	220295	1730	0	0
T5	289489	5588	0	0
T6	170564	4356	0	0
T7	194548	1103	0	0
T8	265700	7966	0	0
T9	474170	0	0	0
T10	6984	67	0	0
T11	5588	79	0	0
T12	0	832	0	0