Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3515001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4156788

1

T2

886

T3

911

T4

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4317945	1			T1	55		T2	5		T3	53
values[0x0]	1676429	1			T2	418		T3	448		T4	20
values[0x1]	1677415	1			T2	468		T3	440		T4	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2506138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5165651

1

T1

16

T2

888

T3

912

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27703	1			T2	5		T3	4		T4	1
valid_sources[0x01]	27095	1			T2	7		T3	6		T5	5
valid_sources[0x02]	27654	1			T2	1		T5	5		T6	4
valid_sources[0x03]	26996	1			T1	3		T3	5		T5	12
valid_sources[0x04]	26992	1			T2	5		T3	1		T5	3
valid_sources[0x05]	30903	1			T2	1		T3	2		T5	4
valid_sources[0x06]	28612	1			T3	10		T5	3		T6	5
valid_sources[0x07]	28279	1			T3	2		T5	4		T6	6
valid_sources[0x08]	27678	1			T2	6		T3	3		T5	10
valid_sources[0x09]	29010	1			T2	1		T3	1		T5	7
valid_sources[0x0a]	25422	1			T3	14		T5	2		T6	7
valid_sources[0x0b]	32263	1			T2	6		T3	3		T5	3
valid_sources[0x0c]	26066	1			T2	3		T3	7		T5	1
valid_sources[0x0d]	28280	1			T2	7		T5	1		T6	2
valid_sources[0x0e]	28050	1			T2	1		T3	8		T5	3
valid_sources[0x0f]	30127	1			T2	3		T3	6		T5	2
valid_sources[0x10]	26782	1			T2	10		T3	1		T5	5
valid_sources[0x11]	30115	1			T2	2		T3	5		T5	7
valid_sources[0x12]	27625	1			T2	10		T5	5		T6	4
valid_sources[0x13]	36272	1			T2	2		T5	2		T6	3
valid_sources[0x14]	25994	1			T2	8		T5	6		T6	5
valid_sources[0x15]	27956	1			T3	2		T5	7		T6	6
valid_sources[0x16]	29210	1			T2	4		T3	10		T5	6
valid_sources[0x17]	28170	1			T2	4		T3	2		T5	9
valid_sources[0x18]	28145	1			T1	4		T2	3		T5	3
valid_sources[0x19]	27874	1			T2	7		T3	3		T5	4
valid_sources[0x1a]	28595	1			T2	1		T3	7		T5	7
valid_sources[0x1b]	31192	1			T2	4		T3	22		T5	5
valid_sources[0x1c]	32945	1			T2	1		T3	7		T5	9
valid_sources[0x1d]	29248	1			T2	4		T3	11		T5	9
valid_sources[0x1e]	29837	1			T2	5		T3	20		T4	3
valid_sources[0x1f]	26847	1			T2	6		T3	8		T5	7
valid_sources[0x20]	27232	1			T2	5		T3	1		T5	4
valid_sources[0x21]	32259	1			T2	1		T4	1		T5	1
valid_sources[0x22]	29446	1			T2	9		T5	1		T6	4
valid_sources[0x23]	28696	1			T2	3		T3	3		T5	1
valid_sources[0x24]	29004	1			T2	2		T5	1		T6	2
valid_sources[0x25]	29542	1			T2	9		T3	3		T5	12
valid_sources[0x26]	29615	1			T2	16		T5	7		T6	6
valid_sources[0x27]	26767	1			T2	10		T7	2		T8	230
valid_sources[0x28]	30458	1			T4	1		T5	7		T6	2
valid_sources[0x29]	27690	1			T2	15		T3	7		T5	3
valid_sources[0x2a]	27909	1			T2	7		T3	6		T5	3
valid_sources[0x2b]	34803	1			T2	2		T4	1		T6	2
valid_sources[0x2c]	25727	1			T2	4		T5	2		T6	2
valid_sources[0x2d]	39312	1			T3	5		T5	2		T6	7
valid_sources[0x2e]	27829	1			T1	6		T3	1		T6	5
valid_sources[0x2f]	29323	1			T2	1		T3	11		T5	2
valid_sources[0x30]	27715	1			T2	1		T5	6		T6	2
valid_sources[0x31]	28088	1			T1	4		T2	6		T5	6
valid_sources[0x32]	29954	1			T2	8		T3	1		T5	5
valid_sources[0x33]	27597	1			T2	1		T3	2		T5	3
valid_sources[0x34]	33858	1			T2	3		T5	13		T6	3
valid_sources[0x35]	28318	1			T2	5		T3	9		T6	4
valid_sources[0x36]	32290	1			T2	1		T3	8		T5	4
valid_sources[0x37]	28128	1			T2	4		T3	4		T5	2
valid_sources[0x38]	27873	1			T2	1		T3	2		T6	3
valid_sources[0x39]	28783	1			T2	9		T3	2		T5	12
valid_sources[0x3a]	32509	1			T3	7		T5	7		T6	3
valid_sources[0x3b]	28163	1			T3	5		T5	6		T6	1
valid_sources[0x3c]	29750	1			T2	1		T3	2		T5	11
valid_sources[0x3d]	29235	1			T5	7		T6	7		T7	7
valid_sources[0x3e]	28831	1			T2	3		T3	1		T5	1
valid_sources[0x3f]	29750	1			T2	7		T3	10		T4	1
valid_sources[0x40]	26414	1			T2	3		T5	5		T6	3
valid_sources[0x41]	30473	1			T2	6		T3	6		T4	1
valid_sources[0x42]	27801	1			T2	2		T3	1		T5	2
valid_sources[0x43]	25502	1			T2	4		T5	5		T6	8
valid_sources[0x44]	30907	1			T2	3		T3	1		T5	1
valid_sources[0x45]	45591	1			T2	4		T3	2		T5	6
valid_sources[0x46]	28830	1			T2	1		T3	5		T5	11
valid_sources[0x47]	29478	1			T2	5		T3	12		T4	1
valid_sources[0x48]	28394	1			T2	2		T3	9		T6	6
valid_sources[0x49]	34723	1			T2	1		T3	1		T5	16
valid_sources[0x4a]	31878	1			T2	1		T6	5		T7	4
valid_sources[0x4b]	27858	1			T2	3		T3	3		T6	3
valid_sources[0x4c]	29164	1			T2	1		T3	5		T5	4
valid_sources[0x4d]	33597	1			T2	3		T3	5		T5	1
valid_sources[0x4e]	27879	1			T1	1		T2	2		T3	5
valid_sources[0x4f]	27719	1			T2	1		T3	6		T5	10
valid_sources[0x50]	88058	1			T2	6		T3	7		T5	3
valid_sources[0x51]	26985	1			T2	2		T5	2		T6	1
valid_sources[0x52]	29859	1			T5	11		T6	4		T7	8
valid_sources[0x53]	25960	1			T2	3		T3	13		T5	11
valid_sources[0x54]	27674	1			T1	2		T2	1		T3	3
valid_sources[0x55]	35594	1			T3	6		T5	6		T6	1
valid_sources[0x56]	30014	1			T2	2		T5	4		T6	2
valid_sources[0x57]	33241	1			T2	5		T3	8		T5	4
valid_sources[0x58]	34460	1			T2	6		T3	2		T5	10
valid_sources[0x59]	27496	1			T3	5		T5	3		T6	5
valid_sources[0x5a]	31442	1			T3	5		T6	8		T7	2
valid_sources[0x5b]	30311	1			T3	9		T5	1		T6	11
valid_sources[0x5c]	32764	1			T2	10		T3	1		T5	2
valid_sources[0x5d]	28365	1			T2	12		T3	4		T5	1
valid_sources[0x5e]	33358	1			T3	1		T5	15		T7	1
valid_sources[0x5f]	27364	1			T2	1		T3	7		T4	1
valid_sources[0x60]	34390	1			T3	5		T5	6		T6	1
valid_sources[0x61]	28915	1			T3	2		T5	4		T6	4
valid_sources[0x62]	30668	1			T2	4		T5	3		T6	2
valid_sources[0x63]	28879	1			T2	7		T3	1		T5	3
valid_sources[0x64]	25461	1			T2	10		T3	1		T4	2
valid_sources[0x65]	67570	1			T2	12		T5	1		T6	1
valid_sources[0x66]	26018	1			T2	2		T3	1		T5	6
valid_sources[0x67]	27815	1			T2	6		T4	2		T5	5
valid_sources[0x68]	28476	1			T1	4		T3	2		T5	3
valid_sources[0x69]	31288	1			T3	4		T5	10		T6	5
valid_sources[0x6a]	26363	1			T2	10		T3	2		T5	3
valid_sources[0x6b]	28578	1			T2	3		T6	3		T7	1
valid_sources[0x6c]	27710	1			T2	2		T4	1		T5	3
valid_sources[0x6d]	29589	1			T2	3		T3	1		T5	2
valid_sources[0x6e]	27023	1			T2	2		T3	6		T5	9
valid_sources[0x6f]	32811	1			T2	7		T3	12		T5	6
valid_sources[0x70]	28761	1			T3	2		T6	4		T8	280
valid_sources[0x71]	27662	1			T3	5		T5	9		T6	3
valid_sources[0x72]	28780	1			T2	5		T3	2		T5	4
valid_sources[0x73]	27812	1			T2	9		T3	6		T5	2
valid_sources[0x74]	30814	1			T2	1		T4	1		T5	1
valid_sources[0x75]	28364	1			T2	9		T3	10		T5	2
valid_sources[0x76]	27958	1			T1	7		T2	3		T3	5
valid_sources[0x77]	39106	1			T2	2		T3	5		T5	4
valid_sources[0x78]	26838	1			T1	6		T3	4		T5	3
valid_sources[0x79]	31910	1			T2	1		T3	1		T4	2
valid_sources[0x7a]	29697	1			T2	2		T3	2		T4	1
valid_sources[0x7b]	28565	1			T2	7		T4	1		T5	2
valid_sources[0x7c]	26793	1			T2	6		T5	10		T6	2
valid_sources[0x7d]	28801	1			T3	7		T5	7		T7	1
valid_sources[0x7e]	34103	1			T2	4		T3	1		T5	1
valid_sources[0x7f]	29700	1			T2	4		T3	1		T5	4
valid_sources[0x80]	29091	1			T2	5		T5	6		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1121419

1

T2

3

T3

26

T4

1

values[0x0]

all_enables

biggest_size

1529207

1

T2

416

T3

446

T4

17

values[0x1]

all_enables

biggest_size

1506162

1

T2

467

T3

439

T4

14