Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3537716

1

T1

55

T2

5

T3

30

full_word

4158177

1

T2

886

T3

911

T4

32

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7695583	1			T1	55		T2	891		T3	941
auto[TlIntgErrCmd]	111	1			T66	14		T98	2		T99	9
auto[TlIntgErrData]	114	1			T66	9		T98	3		T99	4
auto[TlIntgErrBoth]	85	1			T66	7		T98	5		T99	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4321848

1

T1

55

T2

5

T3

53

auto[1]

3374045

1

T2

886

T3

888

T4

40

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3199953	1			T1	55		T2	2		T3	27
auto[TlIntgErrNone]	partial	auto[1]	337474	1			T2	3		T3	3		T4	9
auto[TlIntgErrNone]	full_word	auto[0]	1121748	1			T2	3		T3	26		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3036408	1			T2	883		T3	885		T4	31
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T66	7		T98	1		T99	4
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T66	6		T99	5		T113	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T66	1		T98	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T172	1		T173	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T66	5		T98	2		T99	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T66	4		T98	1		T113	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T111	1		T174	1		T175	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T99	1		T113	1		T176	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T66	4		T98	2		T99	5
auto[TlIntgErrBoth]	partial	auto[1]	38	1			T66	3		T98	1		T99	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T98	1		T177	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T98	1		T177	1		T178	1