Group : spi_device_env_pkg::busy_blocks_command_cg
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Group : spi_device_env_pkg::busy_blocks_command_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
spi_device_env_pkg.en4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.ex4b_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.upload_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wrdi_block_cmd_cg 100.00 1 100 1 64 64
spi_device_env_pkg.wren_block_cmd_cg 100.00 1 100 1 64 64




Group Instance : spi_device_env_pkg.en4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.en4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.en4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.ex4b_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.ex4b_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.upload_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.upload_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.upload_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wrdi_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wrdi_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0



Group Instance : spi_device_env_pkg.wren_block_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_env_pkg.wren_block_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance spi_device_env_pkg.wren_block_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_blocked_or_allowed 2 0 2 100.00 100 1 1 0


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 20 1 T14 1 T93 1 T42 1
allowed 1409 1 T8 16 T9 1 T14 4


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 39 1 T39 1 T38 1 T84 5
allowed 1425 1 T8 17 T9 1 T14 1


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 129 1 T14 2 T84 8 T42 2
allowed 4298 1 T8 44 T9 4 T14 14


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 37 1 T14 2 T93 2 T42 4
allowed 1431 1 T8 21 T9 3 T22 2


Summary for Variable cp_blocked_or_allowed

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_blocked_or_allowed

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
blocked 19 1 T93 2 T46 1 T179 2
allowed 1410 1 T8 11 T9 5 T14 5

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