Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	2741566	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	2741566	0	0
T2	50131	1663	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	1663	0	0
T7	61224	832	0	0
T8	312705	23289	0	0
T9	349069	4167	0	0
T10	3520	0	0	0
T11	18489	1663	0	0
T13	0	1663	0	0
T14	0	4159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	2879989	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	2879989	0	0
T2	50131	832	0	0
T3	40924	3843	0	0
T4	5957	0	0	0
T5	17678	3758	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	17472	0	0
T9	349069	5607	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	178441	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	178441	0	0
T8	312705	2241	0	0
T9	349069	750	0	0
T10	3520	0	0	0
T11	18489	0	0	0
T12	64868	0	0	0
T13	78146	0	0	0
T14	98351	288	0	0
T22	557974	1181	0	0
T23	7629	0	0	0
T24	70718	0	0	0
T25	0	1028	0	0
T27	0	888	0	0
T31	0	1	0	0
T38	0	160	0	0
T39	0	1	0	0
T40	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	390068	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	390068	0	0
T8	312705	2241	0	0
T9	349069	3414	0	0
T10	3520	0	0	0
T11	18489	0	0	0
T12	64868	0	0	0
T13	78146	0	0	0
T14	98351	288	0	0
T22	557974	5102	0	0
T23	7629	0	0	0
T24	70718	0	0	0
T25	0	1027	0	0
T27	0	3997	0	0
T31	0	6	0	0
T38	0	496	0	0
T39	0	1	0	0
T40	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	6088098	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	6088098	0	0
T1	1166	55	0	0
T2	50131	59	0	0
T3	40924	109	0	0
T4	5957	41	0	0
T5	17678	401	0	0
T6	7494	55	0	0
T7	61224	142	0	0
T8	312705	46910	0	0
T9	349069	9275	0	0
T10	3520	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426381931	12397487	0	0
DepthKnown_A	426381931	426260653	0	0
RvalidKnown_A	426381931	426260653	0	0
WreadyKnown_A	426381931	426260653	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	12397487	0	0
T1	1166	55	0	0
T2	50131	152	0	0
T3	40924	463	0	0
T4	5957	41	0	0
T5	17678	1757	0	0
T6	7494	55	0	0
T7	61224	142	0	0
T8	312705	46676	0	0
T9	349069	36765	0	0
T10	3520	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426381931	426260653	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0