Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T22
1	0	Covered	T8,T9,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Unreachable
1	1	Covered	T8,T9,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T8,T9,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T8,T9,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	700234854	560589898	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	700234854	3522223	0	0
GntImpliesValid_A	700234854	3522223	0	0
GrantKnown_A	700234854	560589898	0	0
IdxKnown_A	700234854	560589898	0	0
IndexIsCorrect_A	700234854	3522223	0	0
LockArbDecision_A	700234854	0	0	0
NoReadyValidNoGrant_A	700234854	0	0	0
ReadyAndValidImplyGrant_A	700234854	3522223	0	0
ReqAndReadyImplyGrant_A	700234854	3522223	0	0
ReqImpliesValid_A	700234854	3522223	0	0
ReqStaysHighUntilGranted0_M	700234854	0	0	0
RoundRobin_A	700234854	5	0	955
ValidKnown_A	700234854	560589898	0	0
gen_data_port_assertion.DataFlow_A	700234854	3522223	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	560589898	0	0
T1	1166	1069	0	0
T2	96883	96794	0	0
T3	130388	130325	0	0
T4	7829	6815	0	0
T5	46456	31998	0	0
T6	11670	9499	0	0
T7	117304	89188	0	0
T8	2306833	1297579	0	0
T9	1000837	670842	0	0
T10	3520	3465	0	0
T11	14994	7374	0	0
T12	73608	33976	0	0
T13	18645	18645	0	0
T14	193345	192571	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	560589898	0	0
T1	1166	1069	0	0
T2	96883	96794	0	0
T3	130388	130325	0	0
T4	7829	6815	0	0
T5	46456	31998	0	0
T6	11670	9499	0	0
T7	117304	89188	0	0
T8	2306833	1297579	0	0
T9	1000837	670842	0	0
T10	3520	3465	0	0
T11	14994	7374	0	0
T12	73608	33976	0	0
T13	18645	18645	0	0
T14	193345	192571	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	560589898	0	0
T1	1166	1069	0	0
T2	96883	96794	0	0
T3	130388	130325	0	0
T4	7829	6815	0	0
T5	46456	31998	0	0
T6	11670	9499	0	0
T7	117304	89188	0	0
T8	2306833	1297579	0	0
T9	1000837	670842	0	0
T10	3520	3465	0	0
T11	14994	7374	0	0
T12	73608	33976	0	0
T13	18645	18645	0	0
T14	193345	192571	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	5	0	955
T8	312705	1	0	1
T9	349069	0	0	1
T10	3520	0	0	1
T11	18489	0	0	1
T12	64868	0	0	1
T13	78146	0	0	1
T14	98351	0	0	1
T22	557974	0	0	1
T23	7629	0	0	1
T24	70718	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	560589898	0	0
T1	1166	1069	0	0
T2	96883	96794	0	0
T3	130388	130325	0	0
T4	7829	6815	0	0
T5	46456	31998	0	0
T6	11670	9499	0	0
T7	117304	89188	0	0
T8	2306833	1297579	0	0
T9	1000837	670842	0	0
T10	3520	3465	0	0
T11	14994	7374	0	0
T12	73608	33976	0	0
T13	18645	18645	0	0
T14	193345	192571	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	700234854	3522223	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	2306833	36546	0	0
T9	1000837	10583	0	0
T10	3520	0	0	0
T11	33483	832	0	0
T12	73608	0	0	0
T13	37290	832	0	0
T14	386690	5375	0	0
T22	949540	8512	0	0
T23	36604	0	0	0
T24	30136	0	0	0
T25	0	15381	0	0
T27	0	5396	0	0
T29	0	4547	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T41	0	5471	0	0
T44	12880	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T22
1	0	Covered	T8,T9,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Unreachable
1	1	Covered	T8,T9,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T9,T22
0	0	1	Unreachable
0	0	0	Covered	T4,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T22
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138245491	26336655	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	138245491	609970	0	0
GntImpliesValid_A	138245491	609970	0	0
GrantKnown_A	138245491	26336655	0	0
IdxKnown_A	138245491	26336655	0	0
IndexIsCorrect_A	138245491	609970	0	0
LockArbDecision_A	138245491	0	0	0
NoReadyValidNoGrant_A	138245491	0	0	0
ReadyAndValidImplyGrant_A	138245491	609970	0	0
ReqAndReadyImplyGrant_A	138245491	609970	0	0
ReqImpliesValid_A	138245491	609970	0	0
ReqStaysHighUntilGranted0_M	138245491	0	0	0
RoundRobin_A	138245491	0	0	0
ValidKnown_A	138245491	26336655	0	0
gen_data_port_assertion.DataFlow_A	138245491	609970	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	26336655	0	0
T4	936	936	0	0
T5	14389	0	0	0
T6	2088	0	0	0
T7	28040	0	0	0
T8	997064	212672	0	0
T9	325884	164960	0	0
T11	7497	0	0	0
T12	36804	33976	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	26336655	0	0
T4	936	936	0	0
T5	14389	0	0	0
T6	2088	0	0	0
T7	28040	0	0	0
T8	997064	212672	0	0
T9	325884	164960	0	0
T11	7497	0	0	0
T12	36804	33976	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	26336655	0	0
T4	936	936	0	0
T5	14389	0	0	0
T6	2088	0	0	0
T7	28040	0	0	0
T8	997064	212672	0	0
T9	325884	164960	0	0
T11	7497	0	0	0
T12	36804	33976	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	26336655	0	0
T4	936	936	0	0
T5	14389	0	0	0
T6	2088	0	0	0
T7	28040	0	0	0
T8	997064	212672	0	0
T9	325884	164960	0	0
T11	7497	0	0	0
T12	36804	33976	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	0	275256	0	0
T25	0	60040	0	0
T27	0	73168	0	0
T28	0	360	0	0
T31	0	72	0	0
T32	0	304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	609970	0	0
T8	997064	8410	0	0
T9	325884	3825	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	0	0	0
T22	474770	6580	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	2266	0	0
T27	0	3358	0	0
T29	0	4499	0	0
T30	0	3118	0	0
T31	0	4	0	0
T32	0	8	0	0
T41	0	5471	0	0
T44	6440	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T8,T9,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T8,T9,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T9,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138245491	110592402	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	138245491	768787	0	0
GntImpliesValid_A	138245491	768787	0	0
GrantKnown_A	138245491	110592402	0	0
IdxKnown_A	138245491	110592402	0	0
IndexIsCorrect_A	138245491	768787	0	0
LockArbDecision_A	138245491	0	0	0
NoReadyValidNoGrant_A	138245491	0	0	0
ReadyAndValidImplyGrant_A	138245491	768787	0	0
ReqAndReadyImplyGrant_A	138245491	768787	0	0
ReqImpliesValid_A	138245491	768787	0	0
ReqStaysHighUntilGranted0_M	138245491	0	0	0
RoundRobin_A	138245491	0	0	0
ValidKnown_A	138245491	110592402	0	0
gen_data_port_assertion.DataFlow_A	138245491	768787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	110592402	0	0
T2	46752	46752	0	0
T3	89464	89464	0	0
T4	936	0	0	0
T5	14389	14386	0	0
T6	2088	2088	0	0
T7	28040	28040	0	0
T8	997064	772219	0	0
T9	325884	156899	0	0
T11	7497	7374	0	0
T12	36804	0	0	0
T13	0	18645	0	0
T14	0	192571	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	110592402	0	0
T2	46752	46752	0	0
T3	89464	89464	0	0
T4	936	0	0	0
T5	14389	14386	0	0
T6	2088	2088	0	0
T7	28040	28040	0	0
T8	997064	772219	0	0
T9	325884	156899	0	0
T11	7497	7374	0	0
T12	36804	0	0	0
T13	0	18645	0	0
T14	0	192571	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	110592402	0	0
T2	46752	46752	0	0
T3	89464	89464	0	0
T4	936	0	0	0
T5	14389	14386	0	0
T6	2088	2088	0	0
T7	28040	28040	0	0
T8	997064	772219	0	0
T9	325884	156899	0	0
T11	7497	7374	0	0
T12	36804	0	0	0
T13	0	18645	0	0
T14	0	192571	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	110592402	0	0
T2	46752	46752	0	0
T3	89464	89464	0	0
T4	936	0	0	0
T5	14389	14386	0	0
T6	2088	2088	0	0
T7	28040	28040	0	0
T8	997064	772219	0	0
T9	325884	156899	0	0
T11	7497	7374	0	0
T12	36804	0	0	0
T13	0	18645	0	0
T14	0	192571	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138245491	768787	0	0
T8	997064	5948	0	0
T9	325884	2220	0	0
T11	7497	0	0	0
T12	36804	0	0	0
T13	18645	0	0	0
T14	193345	1746	0	0
T22	474770	1932	0	0
T23	18302	0	0	0
T24	15068	0	0	0
T25	0	13115	0	0
T27	0	2038	0	0
T29	0	48	0	0
T38	0	3445	0	0
T39	0	11	0	0
T40	0	97	0	0
T44	6440	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423743872	423660841	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	423743872	2143466	0	0
GntImpliesValid_A	423743872	2143466	0	0
GrantKnown_A	423743872	423660841	0	0
IdxKnown_A	423743872	423660841	0	0
IndexIsCorrect_A	423743872	2143466	0	0
LockArbDecision_A	423743872	0	0	0
NoReadyValidNoGrant_A	423743872	0	0	0
ReadyAndValidImplyGrant_A	423743872	2143466	0	0
ReqAndReadyImplyGrant_A	423743872	2143466	0	0
ReqImpliesValid_A	423743872	2143466	0	0
ReqStaysHighUntilGranted0_M	423743872	0	0	0
RoundRobin_A	423743872	5	0	955
ValidKnown_A	423743872	423660841	0	0
gen_data_port_assertion.DataFlow_A	423743872	2143466	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	423660841	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	423660841	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	423660841	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	5	0	955
T8	312705	1	0	1
T9	349069	0	0	1
T10	3520	0	0	1
T11	18489	0	0	1
T12	64868	0	0	1
T13	78146	0	0	1
T14	98351	0	0	1
T22	557974	0	0	1
T23	7629	0	0	1
T24	70718	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	423660841	0	0
T1	1166	1069	0	0
T2	50131	50042	0	0
T3	40924	40861	0	0
T4	5957	5879	0	0
T5	17678	17612	0	0
T6	7494	7411	0	0
T7	61224	61148	0	0
T8	312705	312688	0	0
T9	349069	348983	0	0
T10	3520	3465	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423743872	2143466	0	0
T2	50131	832	0	0
T3	40924	832	0	0
T4	5957	0	0	0
T5	17678	832	0	0
T6	7494	832	0	0
T7	61224	832	0	0
T8	312705	22188	0	0
T9	349069	4538	0	0
T10	3520	0	0	0
T11	18489	832	0	0
T13	0	832	0	0
T14	0	3629	0	0