Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3722100	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4369070

1

T1

11341

T2

927

T3

746

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4361097	1			T1	1413		T2	69		T3	1
values[0x0]	1863680	1			T1	5274		T2	444		T3	438
values[0x1]	1866393	1			T1	5291		T2	451		T3	447

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2626463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5464707

1

T1

11491

T2

931

T3

798

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29451	1			T3	3		T6	3		T7	3
valid_sources[0x01]	33341	1			T3	1		T6	2		T7	5
valid_sources[0x02]	31100	1			T1	1		T3	3		T7	6
valid_sources[0x03]	36879	1			T3	1		T6	11		T7	5
valid_sources[0x04]	30957	1			T1	1		T3	1		T6	9
valid_sources[0x05]	41749	1			T2	19		T3	3		T6	4
valid_sources[0x06]	30225	1			T1	3		T2	2		T3	1
valid_sources[0x07]	29643	1			T3	1		T7	4		T9	31
valid_sources[0x08]	29364	1			T3	5		T6	8		T7	7
valid_sources[0x09]	29134	1			T1	464		T3	2		T6	2
valid_sources[0x0a]	35633	1			T1	20		T3	8		T6	4
valid_sources[0x0b]	38338	1			T1	1		T2	3		T3	2
valid_sources[0x0c]	32739	1			T1	1		T3	2		T6	1
valid_sources[0x0d]	32161	1			T2	11		T3	3		T6	6
valid_sources[0x0e]	31566	1			T1	1		T2	4		T3	6
valid_sources[0x0f]	30931	1			T3	1		T9	43		T12	10
valid_sources[0x10]	28688	1			T1	693		T3	5		T6	7
valid_sources[0x11]	29874	1			T3	1		T7	3		T9	40
valid_sources[0x12]	33077	1			T3	6		T6	17		T7	4
valid_sources[0x13]	31841	1			T2	33		T3	3		T6	13
valid_sources[0x14]	30225	1			T2	4		T3	1		T6	4
valid_sources[0x15]	29611	1			T2	5		T3	1		T6	11
valid_sources[0x16]	29073	1			T3	4		T7	3		T9	41
valid_sources[0x17]	32302	1			T3	2		T7	5		T9	36
valid_sources[0x18]	33482	1			T2	12		T3	7		T7	4
valid_sources[0x19]	30656	1			T2	22		T3	2		T6	8
valid_sources[0x1a]	30147	1			T2	13		T3	5		T6	13
valid_sources[0x1b]	30122	1			T2	7		T3	2		T6	2
valid_sources[0x1c]	29015	1			T1	1		T2	8		T3	2
valid_sources[0x1d]	32238	1			T2	1		T3	5		T7	4
valid_sources[0x1e]	30237	1			T2	2		T3	1		T6	8
valid_sources[0x1f]	30061	1			T3	3		T6	17		T7	2
valid_sources[0x20]	31388	1			T3	3		T6	5		T7	2
valid_sources[0x21]	31543	1			T2	5		T3	5		T6	3
valid_sources[0x22]	30246	1			T1	551		T3	6		T7	5
valid_sources[0x23]	29835	1			T2	8		T6	10		T9	40
valid_sources[0x24]	30038	1			T3	2		T6	17		T7	3
valid_sources[0x25]	34762	1			T1	1		T2	8		T3	3
valid_sources[0x26]	35561	1			T2	2		T3	4		T6	2
valid_sources[0x27]	31760	1			T1	2		T2	12		T3	5
valid_sources[0x28]	32842	1			T1	416		T3	4		T6	7
valid_sources[0x29]	32887	1			T1	469		T3	2		T6	10
valid_sources[0x2a]	30234	1			T1	1		T2	1		T3	5
valid_sources[0x2b]	29211	1			T2	1		T3	1		T6	13
valid_sources[0x2c]	27680	1			T1	4		T3	7		T6	2
valid_sources[0x2d]	27752	1			T2	9		T3	4		T6	7
valid_sources[0x2e]	29339	1			T3	3		T6	2		T7	2
valid_sources[0x2f]	30736	1			T2	6		T3	3		T4	2
valid_sources[0x30]	30782	1			T3	4		T6	24		T7	3
valid_sources[0x31]	32478	1			T3	4		T6	4		T7	5
valid_sources[0x32]	28015	1			T1	1		T3	2		T6	1
valid_sources[0x33]	32278	1			T3	12		T6	2		T7	3
valid_sources[0x34]	32143	1			T3	7		T6	3		T7	4
valid_sources[0x35]	33165	1			T1	1		T2	6		T6	6
valid_sources[0x36]	33752	1			T2	19		T3	2		T6	4
valid_sources[0x37]	35116	1			T2	9		T3	1		T6	1
valid_sources[0x38]	28845	1			T2	10		T3	3		T7	4
valid_sources[0x39]	30366	1			T1	1		T2	1		T3	1
valid_sources[0x3a]	34370	1			T3	1		T6	13		T7	2
valid_sources[0x3b]	27987	1			T2	18		T3	1		T6	7
valid_sources[0x3c]	29374	1			T1	1		T3	1		T7	1
valid_sources[0x3d]	29475	1			T1	1		T2	13		T3	4
valid_sources[0x3e]	29066	1			T2	4		T3	3		T6	20
valid_sources[0x3f]	32568	1			T1	1		T3	8		T6	14
valid_sources[0x40]	32043	1			T3	3		T6	6		T7	3
valid_sources[0x41]	31997	1			T2	8		T3	4		T7	7
valid_sources[0x42]	28584	1			T2	6		T3	2		T7	2
valid_sources[0x43]	36456	1			T2	5		T3	2		T6	15
valid_sources[0x44]	31102	1			T1	1		T3	2		T6	6
valid_sources[0x45]	34646	1			T3	5		T6	4		T7	5
valid_sources[0x46]	30085	1			T2	2		T3	2		T6	13
valid_sources[0x47]	32471	1			T3	2		T9	22		T12	3
valid_sources[0x48]	28670	1			T2	7		T3	5		T6	7
valid_sources[0x49]	33136	1			T2	1		T3	4		T6	8
valid_sources[0x4a]	28544	1			T3	8		T6	6		T7	4
valid_sources[0x4b]	30251	1			T3	4		T7	4		T9	31
valid_sources[0x4c]	30919	1			T3	2		T6	3		T7	4
valid_sources[0x4d]	29503	1			T3	6		T6	24		T7	11
valid_sources[0x4e]	29889	1			T3	7		T6	1		T7	9
valid_sources[0x4f]	30453	1			T1	673		T2	2		T6	13
valid_sources[0x50]	30099	1			T1	1		T2	15		T3	2
valid_sources[0x51]	29346	1			T2	4		T3	2		T6	19
valid_sources[0x52]	29077	1			T3	3		T7	2		T9	29
valid_sources[0x53]	33887	1			T3	4		T6	7		T7	1
valid_sources[0x54]	33673	1			T1	1		T2	6		T3	1
valid_sources[0x55]	30504	1			T3	5		T6	13		T7	1
valid_sources[0x56]	32130	1			T3	1		T6	6		T7	10
valid_sources[0x57]	30372	1			T1	1		T2	10		T3	1
valid_sources[0x58]	35159	1			T3	2		T6	25		T7	2
valid_sources[0x59]	32460	1			T2	12		T3	1		T6	6
valid_sources[0x5a]	28286	1			T3	5		T6	9		T7	5
valid_sources[0x5b]	29121	1			T2	5		T3	6		T6	4
valid_sources[0x5c]	30175	1			T2	5		T3	1		T7	3
valid_sources[0x5d]	32178	1			T2	2		T3	4		T6	2
valid_sources[0x5e]	31110	1			T2	23		T3	3		T6	22
valid_sources[0x5f]	28925	1			T1	679		T3	5		T7	1
valid_sources[0x60]	30528	1			T1	7		T3	2		T6	6
valid_sources[0x61]	31576	1			T3	2		T6	1		T7	6
valid_sources[0x62]	28458	1			T3	2		T6	10		T7	4
valid_sources[0x63]	36645	1			T1	1		T3	5		T6	9
valid_sources[0x64]	31823	1			T1	1		T3	2		T7	6
valid_sources[0x65]	31566	1			T1	1		T3	4		T6	7
valid_sources[0x66]	33391	1			T1	22		T2	14		T3	3
valid_sources[0x67]	33675	1			T2	3		T3	5		T6	2
valid_sources[0x68]	28672	1			T3	4		T7	5		T9	32
valid_sources[0x69]	30171	1			T2	8		T7	2		T9	45
valid_sources[0x6a]	29101	1			T3	4		T6	7		T7	5
valid_sources[0x6b]	32144	1			T1	1		T3	2		T6	5
valid_sources[0x6c]	28998	1			T2	1		T3	5		T6	22
valid_sources[0x6d]	34374	1			T1	1		T2	2		T3	5
valid_sources[0x6e]	31861	1			T1	3		T2	5		T3	7
valid_sources[0x6f]	31208	1			T2	1		T3	6		T7	11
valid_sources[0x70]	30275	1			T2	12		T3	5		T5	455
valid_sources[0x71]	30839	1			T2	5		T3	4		T6	17
valid_sources[0x72]	36351	1			T2	14		T3	4		T6	4
valid_sources[0x73]	33614	1			T3	5		T6	7		T7	5
valid_sources[0x74]	29463	1			T2	7		T3	8		T6	17
valid_sources[0x75]	40498	1			T1	2		T2	15		T3	5
valid_sources[0x76]	30364	1			T1	1		T3	2		T6	4
valid_sources[0x77]	33422	1			T2	2		T3	5		T6	11
valid_sources[0x78]	30080	1			T3	2		T6	13		T7	7
valid_sources[0x79]	31376	1			T3	4		T7	3		T9	54
valid_sources[0x7a]	29827	1			T1	417		T2	7		T3	9
valid_sources[0x7b]	32453	1			T2	9		T3	2		T8	2
valid_sources[0x7c]	31965	1			T2	6		T3	1		T6	11
valid_sources[0x7d]	32905	1			T3	4		T6	5		T7	4
valid_sources[0x7e]	54619	1			T3	3		T6	11		T7	4
valid_sources[0x7f]	30023	1			T3	2		T6	2		T7	1
valid_sources[0x80]	31393	1			T3	7		T6	1		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

988049

1

T1

824

T2

36

T5

8

values[0x0]

all_enables

biggest_size

1702249

1

T1

5256

T2

443

T3

374

values[0x1]

all_enables

biggest_size

1678772

1

T1

5261

T2

448

T3

372