Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3742376

1

T1

637

T2

37

T3

140

full_word

4370194

1

T1

11341

T2

927

T3

746

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8112200	1			T1	11978		T2	964		T3	886
auto[TlIntgErrCmd]	136	1			T74	4		T75	2		T76	8
auto[TlIntgErrData]	127	1			T74	3		T75	5		T76	8
auto[TlIntgErrBoth]	107	1			T74	3		T75	3		T76	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4364272

1

T1

1413

T2

69

T3

1

auto[1]

3748298

1

T1

10565

T2

895

T3

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3375790	1			T1	589		T2	33		T3	1
auto[TlIntgErrNone]	partial	auto[1]	366248	1			T1	48		T2	4		T3	139
auto[TlIntgErrNone]	full_word	auto[0]	988295	1			T1	824		T2	36		T5	8
auto[TlIntgErrNone]	full_word	auto[1]	3381867	1			T1	10517		T2	891		T3	746
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T74	2		T76	6		T104	7
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T75	2		T76	2		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T74	2		T161	1		T162	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T163	1		T162	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T74	2		T75	3		T76	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T75	2		T76	3		T104	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T74	1		T162	2		T165	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T76	1		T123	1		T162	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T75	3		T104	2		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T74	3		T76	4		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T164	1		T166	1		T167	1