Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	677453881	3554279	0	0
gen_wmask[1].MaskCheckPortA_A	677453881	3554279	0	0
gen_wmask[2].MaskCheckPortA_A	677453881	3554279	0	0
gen_wmask[3].MaskCheckPortA_A	677453881	3554279	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677453881	3554279	0	0
T1	466052	15030	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12340	0	0
T9	662245	10429	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	493	832	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0
T53	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677453881	3554279	0	0
T1	466052	15030	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12340	0	0
T9	662245	10429	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	493	832	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0
T53	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677453881	3554279	0	0
T1	466052	15030	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12340	0	0
T9	662245	10429	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	493	832	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0
T53	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677453881	3554279	0	0
T1	466052	15030	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12340	0	0
T9	662245	10429	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	493	832	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0
T53	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	514856358	2182531	0	0
gen_wmask[1].MaskCheckPortA_A	514856358	2182531	0	0
gen_wmask[2].MaskCheckPortA_A	514856358	2182531	0	0
gen_wmask[3].MaskCheckPortA_A	514856358	2182531	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2182531	0	0
T1	362618	9984	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7488	0	0
T9	155707	5824	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2182531	0	0
T1	362618	9984	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7488	0	0
T9	155707	5824	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2182531	0	0
T1	362618	9984	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7488	0	0
T9	155707	5824	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2182531	0	0
T1	362618	9984	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7488	0	0
T9	155707	5824	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	162597523	1371748	0	0
gen_wmask[1].MaskCheckPortA_A	162597523	1371748	0	0
gen_wmask[2].MaskCheckPortA_A	162597523	1371748	0	0
gen_wmask[3].MaskCheckPortA_A	162597523	1371748	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	1371748	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	1371748	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	1371748	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	1371748	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	18921	0	0
T32	0	5855	0	0
T33	0	2393	0	0
T34	0	4453	0	0
T37	0	6739	0	0
T39	0	8681	0	0
T44	0	4	0	0