Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1544569074	2933	0	0
SrcPulseCheck_M	487792569	2933	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544569074	2933	0	0
T1	362618	7	0	0
T2	65056	0	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	0	0	0
T6	361481	0	0	0
T7	50048	0	0	0
T8	235434	12	0	0
T9	155707	10	0	0
T10	2222	0	0	0
T13	59928	7	0	0
T14	0	22	0	0
T25	0	13	0	0
T31	5040	0	0	0
T32	808486	22	0	0
T33	928514	0	0	0
T34	0	1	0	0
T37	0	13	0	0
T39	0	16	0	0
T44	0	2	0	0
T45	95718	1	0	0
T46	0	6	0	0
T47	0	7	0	0
T48	754408	0	0	0
T49	436780	0	0	0
T71	2102	0	0	0
T110	153830	0	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	7	0	0
T146	0	7	0	0
T147	0	7	0	0
T148	0	7	0	0
T149	0	8	0	0
T150	69586	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	487792569	2933	0	0
T1	103434	7	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	12	0	0
T9	506538	10	0	0
T11	25094	0	0	0
T12	493	0	0	0
T13	53146	7	0	0
T14	0	22	0	0
T25	0	13	0	0
T31	1440	0	0	0
T32	1298640	22	0	0
T33	175326	0	0	0
T34	0	1	0	0
T37	0	13	0	0
T39	0	16	0	0
T44	0	2	0	0
T45	12776	1	0	0
T46	0	6	0	0
T47	0	7	0	0
T48	149994	0	0	0
T49	52204	0	0	0
T50	262216	0	0	0
T110	18560	0	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	7	0	0
T146	0	7	0	0
T147	0	7	0	0
T148	0	7	0	0
T149	0	8	0	0
T150	15840	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T45,T46
1	0	Covered	T13,T45,T46
1	1	Covered	T13,T46,T47

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T45,T46
1	0	Covered	T13,T46,T47
1	1	Covered	T13,T45,T46

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	514856358	178	0	0
SrcPulseCheck_M	162597523	178	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	178	0	0
T13	29964	2	0	0
T31	2520	0	0	0
T32	404243	0	0	0
T33	464257	0	0	0
T45	47859	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	377204	0	0	0
T49	218390	0	0	0
T71	1051	0	0	0
T110	76915	0	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	34793	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	178	0	0
T13	26573	2	0	0
T31	720	0	0	0
T32	649320	0	0	0
T33	87663	0	0	0
T45	6388	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	74997	0	0	0
T49	26102	0	0	0
T50	131108	0	0	0
T110	9280	0	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	7920	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T46,T47
1	0	Covered	T13,T46,T47
1	1	Covered	T13,T46,T47

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T46,T47
1	0	Covered	T13,T46,T47
1	1	Covered	T13,T46,T47

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	514856358	324	0	0
SrcPulseCheck_M	162597523	324	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	324	0	0
T13	29964	5	0	0
T31	2520	0	0	0
T32	404243	0	0	0
T33	464257	0	0	0
T45	47859	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T48	377204	0	0	0
T49	218390	0	0	0
T71	1051	0	0	0
T110	76915	0	0	0
T143	0	5	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	5	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	8	0	0
T150	34793	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	324	0	0
T13	26573	5	0	0
T31	720	0	0	0
T32	649320	0	0	0
T33	87663	0	0	0
T45	6388	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T48	74997	0	0	0
T49	26102	0	0	0
T50	131108	0	0	0
T110	9280	0	0	0
T143	0	5	0	0
T144	0	5	0	0
T145	0	5	0	0
T146	0	5	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	8	0	0
T150	7920	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	514856358	2431	0	0
SrcPulseCheck_M	162597523	2431	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2431	0	0
T1	362618	7	0	0
T2	65056	0	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	0	0	0
T6	361481	0	0	0
T7	50048	0	0	0
T8	235434	12	0	0
T9	155707	10	0	0
T10	2222	0	0	0
T14	0	22	0	0
T25	0	13	0	0
T32	0	22	0	0
T34	0	1	0	0
T37	0	13	0	0
T39	0	16	0	0
T44	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	2431	0	0
T1	103434	7	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	12	0	0
T9	506538	10	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	22	0	0
T25	0	13	0	0
T32	0	22	0	0
T34	0	1	0	0
T37	0	13	0	0
T39	0	16	0	0
T44	0	2	0	0