Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	3002364	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	3002364	0	0
T1	362618	14989	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	1663	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	11643	0	0
T9	155707	7486	0	0
T10	2222	0	0	0
T11	0	1663	0	0
T12	0	832	0	0
T53	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	3399468	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	3399468	0	0
T1	362618	27653	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7488	0	0
T9	155707	5824	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	190006	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	190006	0	0
T1	362618	288	0	0
T2	65056	0	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	0	0	0
T6	361481	0	0	0
T7	50048	0	0	0
T8	235434	315	0	0
T9	155707	192	0	0
T10	2222	0	0	0
T14	0	2076	0	0
T25	0	1051	0	0
T32	0	969	0	0
T33	0	620	0	0
T34	0	1085	0	0
T37	0	613	0	0
T39	0	1167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	456017	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	456017	0	0
T1	362618	1289	0	0
T2	65056	0	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	0	0	0
T6	361481	0	0	0
T7	50048	0	0	0
T8	235434	315	0	0
T9	155707	192	0	0
T10	2222	0	0	0
T14	0	9138	0	0
T25	0	4741	0	0
T32	0	969	0	0
T33	0	620	0	0
T34	0	4930	0	0
T37	0	612	0	0
T39	0	5207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	6368592	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	6368592	0	0
T1	362618	1773	0	0
T2	65056	133	0	0
T3	679766	886	0	0
T4	1306	14	0	0
T5	3188	71	0	0
T6	361481	598	0	0
T7	50048	71	0	0
T8	235434	3997	0	0
T9	155707	2797	0	0
T10	2222	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	517372001	14725666	0	0
DepthKnown_A	517372001	517242677	0	0
RvalidKnown_A	517372001	517242677	0	0
WreadyKnown_A	517372001	517242677	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	14725666	0	0
T1	362618	7530	0	0
T2	65056	132	0	0
T3	679766	886	0	0
T4	1306	12	0	0
T5	3188	124	0	0
T6	361481	595	0	0
T7	50048	71	0	0
T8	235434	3997	0	0
T9	155707	2796	0	0
T10	2222	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517372001	517242677	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0