Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T32
1	0	Unreachable
1	1	Covered	T32,T33,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	840051404	675985317	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	840051404	3940101	0	0
GntImpliesValid_A	840051404	3940101	0	0
GrantKnown_A	840051404	675985317	0	0
IdxKnown_A	840051404	675985317	0	0
IndexIsCorrect_A	840051404	3940101	0	0
LockArbDecision_A	840051404	0	0	0
NoReadyValidNoGrant_A	840051404	0	0	0
ReadyAndValidImplyGrant_A	840051404	3940101	0	0
ReqAndReadyImplyGrant_A	840051404	3940101	0	0
ReqImpliesValid_A	840051404	3940101	0	0
ReqStaysHighUntilGranted0_M	840051404	0	0	0
RoundRobin_A	840051404	6	0	954
ValidKnown_A	840051404	675985317	0	0
gen_data_port_assertion.DataFlow_A	840051404	3940101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	675985317	0	0
T1	466052	465457	0	0
T2	84068	84009	0	0
T3	881858	772921	0	0
T4	1306	1244	0	0
T5	3572	3300	0	0
T6	464457	412456	0	0
T7	129620	89526	0	0
T8	1002692	617613	0	0
T9	1168783	660372	0	0
T10	2222	2130	0	0
T11	50188	25094	0	0
T12	986	160	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	675985317	0	0
T1	466052	465457	0	0
T2	84068	84009	0	0
T3	881858	772921	0	0
T4	1306	1244	0	0
T5	3572	3300	0	0
T6	464457	412456	0	0
T7	129620	89526	0	0
T8	1002692	617613	0	0
T9	1168783	660372	0	0
T10	2222	2130	0	0
T11	50188	25094	0	0
T12	986	160	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	675985317	0	0
T1	466052	465457	0	0
T2	84068	84009	0	0
T3	881858	772921	0	0
T4	1306	1244	0	0
T5	3572	3300	0	0
T6	464457	412456	0	0
T7	129620	89526	0	0
T8	1002692	617613	0	0
T9	1168783	660372	0	0
T10	2222	2130	0	0
T11	50188	25094	0	0
T12	986	160	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	6	0	954
T43	198290	0	0	1
T58	338003	1	0	1
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	1685	0	0	1
T64	316325	0	0	1
T65	49951	0	0	1
T66	299164	0	0	1
T67	9337	0	0	1
T68	318958	0	0	1
T69	232849	0	0	1
T70	716879	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	675985317	0	0
T1	466052	465457	0	0
T2	84068	84009	0	0
T3	881858	772921	0	0
T4	1306	1244	0	0
T5	3572	3300	0	0
T6	464457	412456	0	0
T7	129620	89526	0	0
T8	1002692	617613	0	0
T9	1168783	660372	0	0
T10	2222	2130	0	0
T11	50188	25094	0	0
T12	986	160	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840051404	3940101	0	0
T1	466052	15332	0	0
T2	84068	832	0	0
T3	780812	0	0	0
T4	1306	0	0	0
T5	3380	832	0	0
T6	412969	832	0	0
T7	89834	832	0	0
T8	619063	12675	0	0
T9	662245	10639	0	0
T10	2222	0	0	0
T11	25094	832	0	0
T12	0	832	0	0
T14	0	21613	0	0
T15	0	5397	0	0
T25	0	6717	0	0
T27	0	196	0	0
T32	649320	6388	0	0
T33	87663	3723	0	0
T34	202144	6404	0	0
T35	22593	0	0	0
T37	0	7355	0	0
T39	0	10050	0	0
T44	0	4	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T53	0	832	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T32
1	0	Unreachable
1	1	Covered	T32,T33,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T32,T33,T34
0	0	1	Unreachable
0	0	0	Covered	T3,T31,T32

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	162597523	26146788	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	162597523	619765	0	0
GntImpliesValid_A	162597523	619765	0	0
GrantKnown_A	162597523	26146788	0	0
IdxKnown_A	162597523	26146788	0	0
IndexIsCorrect_A	162597523	619765	0	0
LockArbDecision_A	162597523	0	0	0
NoReadyValidNoGrant_A	162597523	0	0	0
ReadyAndValidImplyGrant_A	162597523	619765	0	0
ReqAndReadyImplyGrant_A	162597523	619765	0	0
ReqImpliesValid_A	162597523	619765	0	0
ReqStaysHighUntilGranted0_M	162597523	0	0	0
RoundRobin_A	162597523	0	0	0
ValidKnown_A	162597523	26146788	0	0
gen_data_port_assertion.DataFlow_A	162597523	619765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	26146788	0	0
T3	101046	93232	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	0	0	0
T9	506538	0	0	0
T11	25094	0	0	0
T12	493	0	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	26146788	0	0
T3	101046	93232	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	0	0	0
T9	506538	0	0	0
T11	25094	0	0	0
T12	493	0	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	26146788	0	0
T3	101046	93232	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	0	0	0
T9	506538	0	0	0
T11	25094	0	0	0
T12	493	0	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	26146788	0	0
T3	101046	93232	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	0	0	0
T9	506538	0	0	0
T11	25094	0	0	0
T12	493	0	0	0
T13	26573	0	0	0
T14	0	396576	0	0
T25	0	119184	0	0
T31	0	720	0	0
T32	0	109280	0	0
T33	0	83872	0	0
T34	0	125688	0	0
T35	0	22304	0	0
T37	0	32480	0	0
T39	0	118856	0	0
T48	74997	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	619765	0	0
T14	0	8098	0	0
T15	0	5397	0	0
T25	0	5283	0	0
T27	0	196	0	0
T32	649320	1942	0	0
T33	87663	3723	0	0
T34	202144	5890	0	0
T35	22593	0	0	0
T37	0	1382	0	0
T39	0	4448	0	0
T46	23014	0	0	0
T47	19012	0	0	0
T50	131108	0	0	0
T54	22624	0	0	0
T55	219331	0	0	0
T56	0	3575	0	0
T57	95338	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	162597523	135068989	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	162597523	954609	0	0
GntImpliesValid_A	162597523	954609	0	0
GrantKnown_A	162597523	135068989	0	0
IdxKnown_A	162597523	135068989	0	0
IndexIsCorrect_A	162597523	954609	0	0
LockArbDecision_A	162597523	0	0	0
NoReadyValidNoGrant_A	162597523	0	0	0
ReadyAndValidImplyGrant_A	162597523	954609	0	0
ReqAndReadyImplyGrant_A	162597523	954609	0	0
ReqImpliesValid_A	162597523	954609	0	0
ReqStaysHighUntilGranted0_M	162597523	0	0	0
RoundRobin_A	162597523	0	0	0
ValidKnown_A	162597523	135068989	0	0
gen_data_port_assertion.DataFlow_A	162597523	954609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	135068989	0	0
T1	103434	102926	0	0
T2	19012	19012	0	0
T3	101046	0	0	0
T5	192	192	0	0
T6	51488	51026	0	0
T7	39786	39528	0	0
T8	383629	382187	0	0
T9	506538	504670	0	0
T11	25094	25094	0	0
T12	493	160	0	0
T13	0	26393	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	135068989	0	0
T1	103434	102926	0	0
T2	19012	19012	0	0
T3	101046	0	0	0
T5	192	192	0	0
T6	51488	51026	0	0
T7	39786	39528	0	0
T8	383629	382187	0	0
T9	506538	504670	0	0
T11	25094	25094	0	0
T12	493	160	0	0
T13	0	26393	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	135068989	0	0
T1	103434	102926	0	0
T2	19012	19012	0	0
T3	101046	0	0	0
T5	192	192	0	0
T6	51488	51026	0	0
T7	39786	39528	0	0
T8	383629	382187	0	0
T9	506538	504670	0	0
T11	25094	25094	0	0
T12	493	160	0	0
T13	0	26393	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	135068989	0	0
T1	103434	102926	0	0
T2	19012	19012	0	0
T3	101046	0	0	0
T5	192	192	0	0
T6	51488	51026	0	0
T7	39786	39528	0	0
T8	383629	382187	0	0
T9	506538	504670	0	0
T11	25094	25094	0	0
T12	493	160	0	0
T13	0	26393	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162597523	954609	0	0
T1	103434	5046	0	0
T2	19012	0	0	0
T3	101046	0	0	0
T5	192	0	0	0
T6	51488	0	0	0
T7	39786	0	0	0
T8	383629	4852	0	0
T9	506538	4605	0	0
T11	25094	0	0	0
T12	493	0	0	0
T14	0	13515	0	0
T25	0	1434	0	0
T32	0	4446	0	0
T34	0	514	0	0
T37	0	5973	0	0
T39	0	5602	0	0
T44	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	514856358	514769540	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	514856358	2365727	0	0
GntImpliesValid_A	514856358	2365727	0	0
GrantKnown_A	514856358	514769540	0	0
IdxKnown_A	514856358	514769540	0	0
IndexIsCorrect_A	514856358	2365727	0	0
LockArbDecision_A	514856358	0	0	0
NoReadyValidNoGrant_A	514856358	0	0	0
ReadyAndValidImplyGrant_A	514856358	2365727	0	0
ReqAndReadyImplyGrant_A	514856358	2365727	0	0
ReqImpliesValid_A	514856358	2365727	0	0
ReqStaysHighUntilGranted0_M	514856358	0	0	0
RoundRobin_A	514856358	6	0	954
ValidKnown_A	514856358	514769540	0	0
gen_data_port_assertion.DataFlow_A	514856358	2365727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	514769540	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	514769540	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	514769540	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	6	0	954
T43	198290	0	0	1
T58	338003	1	0	1
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	1685	0	0	1
T64	316325	0	0	1
T65	49951	0	0	1
T66	299164	0	0	1
T67	9337	0	0	1
T68	318958	0	0	1
T69	232849	0	0	1
T70	716879	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	514769540	0	0
T1	362618	362531	0	0
T2	65056	64997	0	0
T3	679766	679689	0	0
T4	1306	1244	0	0
T5	3188	3108	0	0
T6	361481	361430	0	0
T7	50048	49998	0	0
T8	235434	235426	0	0
T9	155707	155702	0	0
T10	2222	2130	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514856358	2365727	0	0
T1	362618	10286	0	0
T2	65056	832	0	0
T3	679766	0	0	0
T4	1306	0	0	0
T5	3188	832	0	0
T6	361481	832	0	0
T7	50048	832	0	0
T8	235434	7823	0	0
T9	155707	6034	0	0
T10	2222	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T53	0	832	0	0