Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
3444 |
0 |
0 |
T75 |
10005 |
1 |
0 |
0 |
T76 |
63468 |
6 |
0 |
0 |
T104 |
71270 |
2 |
0 |
0 |
T105 |
2603 |
70 |
0 |
0 |
T106 |
3866 |
6 |
0 |
0 |
T107 |
20535 |
357 |
0 |
0 |
T108 |
3327 |
9 |
0 |
0 |
T109 |
16312 |
180 |
0 |
0 |
T122 |
60975 |
3 |
0 |
0 |
T123 |
68021 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2083 |
0 |
0 |
T74 |
32446 |
20 |
0 |
0 |
T76 |
63468 |
52 |
0 |
0 |
T104 |
71270 |
65 |
0 |
0 |
T122 |
60975 |
57 |
0 |
0 |
T127 |
4161 |
9 |
0 |
0 |
T129 |
10047 |
13 |
0 |
0 |
T132 |
11145 |
3 |
0 |
0 |
T151 |
19661 |
67 |
0 |
0 |
T152 |
155893 |
252 |
0 |
0 |
T153 |
13122 |
53 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2102 |
0 |
0 |
T74 |
32446 |
28 |
0 |
0 |
T76 |
63468 |
46 |
0 |
0 |
T104 |
71270 |
73 |
0 |
0 |
T122 |
60975 |
54 |
0 |
0 |
T127 |
4161 |
4 |
0 |
0 |
T129 |
10047 |
4 |
0 |
0 |
T132 |
11145 |
7 |
0 |
0 |
T151 |
19661 |
21 |
0 |
0 |
T152 |
155893 |
278 |
0 |
0 |
T153 |
13122 |
55 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2899 |
0 |
0 |
T74 |
32446 |
63 |
0 |
0 |
T76 |
63468 |
81 |
0 |
0 |
T104 |
71270 |
131 |
0 |
0 |
T109 |
16312 |
1 |
0 |
0 |
T127 |
4161 |
21 |
0 |
0 |
T129 |
10047 |
18 |
0 |
0 |
T132 |
11145 |
44 |
0 |
0 |
T151 |
19661 |
54 |
0 |
0 |
T152 |
155893 |
298 |
0 |
0 |
T153 |
13122 |
45 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
13267 |
0 |
0 |
T74 |
32446 |
937 |
0 |
0 |
T76 |
63468 |
508 |
0 |
0 |
T104 |
71270 |
1233 |
0 |
0 |
T122 |
60975 |
884 |
0 |
0 |
T127 |
4161 |
8 |
0 |
0 |
T129 |
10047 |
262 |
0 |
0 |
T132 |
11145 |
159 |
0 |
0 |
T151 |
19661 |
63 |
0 |
0 |
T152 |
155893 |
278 |
0 |
0 |
T153 |
13122 |
34 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
13584 |
0 |
0 |
T74 |
32446 |
466 |
0 |
0 |
T76 |
63468 |
480 |
0 |
0 |
T104 |
71270 |
1465 |
0 |
0 |
T122 |
60975 |
681 |
0 |
0 |
T127 |
4161 |
132 |
0 |
0 |
T129 |
10047 |
14 |
0 |
0 |
T132 |
11145 |
279 |
0 |
0 |
T151 |
19661 |
110 |
0 |
0 |
T152 |
155893 |
270 |
0 |
0 |
T153 |
13122 |
74 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
11410 |
0 |
0 |
T74 |
32446 |
667 |
0 |
0 |
T76 |
63468 |
576 |
0 |
0 |
T104 |
71270 |
868 |
0 |
0 |
T122 |
60975 |
619 |
0 |
0 |
T127 |
4161 |
99 |
0 |
0 |
T129 |
10047 |
138 |
0 |
0 |
T132 |
11145 |
245 |
0 |
0 |
T151 |
19661 |
97 |
0 |
0 |
T152 |
155893 |
206 |
0 |
0 |
T153 |
13122 |
62 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
11398 |
0 |
0 |
T74 |
32446 |
616 |
0 |
0 |
T76 |
63468 |
719 |
0 |
0 |
T104 |
71270 |
1219 |
0 |
0 |
T122 |
60975 |
555 |
0 |
0 |
T127 |
4161 |
103 |
0 |
0 |
T129 |
10047 |
8 |
0 |
0 |
T132 |
11145 |
129 |
0 |
0 |
T151 |
19661 |
62 |
0 |
0 |
T152 |
155893 |
240 |
0 |
0 |
T153 |
13122 |
41 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
12951 |
0 |
0 |
T74 |
32446 |
721 |
0 |
0 |
T76 |
63468 |
842 |
0 |
0 |
T104 |
71270 |
1291 |
0 |
0 |
T122 |
60975 |
813 |
0 |
0 |
T127 |
4161 |
8 |
0 |
0 |
T129 |
10047 |
8 |
0 |
0 |
T132 |
11145 |
6 |
0 |
0 |
T151 |
19661 |
65 |
0 |
0 |
T152 |
155893 |
261 |
0 |
0 |
T153 |
13122 |
27 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
11934 |
0 |
0 |
T74 |
32446 |
104 |
0 |
0 |
T76 |
63468 |
429 |
0 |
0 |
T104 |
71270 |
1672 |
0 |
0 |
T122 |
60975 |
587 |
0 |
0 |
T127 |
4161 |
3 |
0 |
0 |
T129 |
10047 |
248 |
0 |
0 |
T132 |
11145 |
123 |
0 |
0 |
T151 |
19661 |
69 |
0 |
0 |
T152 |
155893 |
249 |
0 |
0 |
T153 |
13122 |
32 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
12386 |
0 |
0 |
T74 |
32446 |
378 |
0 |
0 |
T76 |
63468 |
687 |
0 |
0 |
T104 |
71270 |
1251 |
0 |
0 |
T122 |
60975 |
1017 |
0 |
0 |
T127 |
4161 |
123 |
0 |
0 |
T129 |
10047 |
162 |
0 |
0 |
T132 |
11145 |
87 |
0 |
0 |
T151 |
19661 |
109 |
0 |
0 |
T152 |
155893 |
295 |
0 |
0 |
T153 |
13122 |
18 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
12546 |
0 |
0 |
T74 |
32446 |
619 |
0 |
0 |
T76 |
63468 |
720 |
0 |
0 |
T104 |
71270 |
1559 |
0 |
0 |
T122 |
60975 |
418 |
0 |
0 |
T127 |
4161 |
2 |
0 |
0 |
T129 |
10047 |
217 |
0 |
0 |
T132 |
11145 |
355 |
0 |
0 |
T151 |
19661 |
93 |
0 |
0 |
T152 |
155893 |
255 |
0 |
0 |
T153 |
13122 |
43 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6069 |
0 |
0 |
T74 |
32446 |
140 |
0 |
0 |
T76 |
63468 |
174 |
0 |
0 |
T104 |
71270 |
413 |
0 |
0 |
T122 |
60975 |
247 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
97 |
0 |
0 |
T132 |
11145 |
73 |
0 |
0 |
T151 |
19661 |
65 |
0 |
0 |
T152 |
155893 |
214 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5859 |
0 |
0 |
T74 |
32446 |
292 |
0 |
0 |
T76 |
63468 |
340 |
0 |
0 |
T104 |
71270 |
597 |
0 |
0 |
T122 |
60975 |
175 |
0 |
0 |
T123 |
68021 |
358 |
0 |
0 |
T129 |
10047 |
87 |
0 |
0 |
T132 |
11145 |
115 |
0 |
0 |
T151 |
19661 |
65 |
0 |
0 |
T152 |
155893 |
235 |
0 |
0 |
T153 |
13122 |
49 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5695 |
0 |
0 |
T74 |
32446 |
289 |
0 |
0 |
T76 |
63468 |
291 |
0 |
0 |
T104 |
71270 |
491 |
0 |
0 |
T122 |
60975 |
309 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
70 |
0 |
0 |
T132 |
11145 |
66 |
0 |
0 |
T151 |
19661 |
85 |
0 |
0 |
T152 |
155893 |
224 |
0 |
0 |
T153 |
13122 |
36 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6091 |
0 |
0 |
T74 |
32446 |
230 |
0 |
0 |
T76 |
63468 |
252 |
0 |
0 |
T104 |
71270 |
657 |
0 |
0 |
T122 |
60975 |
196 |
0 |
0 |
T127 |
4161 |
4 |
0 |
0 |
T129 |
10047 |
66 |
0 |
0 |
T132 |
11145 |
64 |
0 |
0 |
T151 |
19661 |
49 |
0 |
0 |
T152 |
155893 |
298 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5541 |
0 |
0 |
T74 |
32446 |
232 |
0 |
0 |
T76 |
63468 |
180 |
0 |
0 |
T104 |
71270 |
487 |
0 |
0 |
T122 |
60975 |
241 |
0 |
0 |
T123 |
68021 |
339 |
0 |
0 |
T129 |
10047 |
52 |
0 |
0 |
T132 |
11145 |
21 |
0 |
0 |
T151 |
19661 |
61 |
0 |
0 |
T152 |
155893 |
277 |
0 |
0 |
T153 |
13122 |
54 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6189 |
0 |
0 |
T74 |
32446 |
333 |
0 |
0 |
T76 |
63468 |
230 |
0 |
0 |
T104 |
71270 |
603 |
0 |
0 |
T122 |
60975 |
262 |
0 |
0 |
T123 |
68021 |
392 |
0 |
0 |
T129 |
10047 |
109 |
0 |
0 |
T132 |
11145 |
133 |
0 |
0 |
T151 |
19661 |
59 |
0 |
0 |
T152 |
155893 |
292 |
0 |
0 |
T153 |
13122 |
28 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6339 |
0 |
0 |
T74 |
32446 |
360 |
0 |
0 |
T76 |
63468 |
311 |
0 |
0 |
T104 |
71270 |
543 |
0 |
0 |
T122 |
60975 |
265 |
0 |
0 |
T127 |
4161 |
32 |
0 |
0 |
T129 |
10047 |
113 |
0 |
0 |
T132 |
11145 |
101 |
0 |
0 |
T151 |
19661 |
74 |
0 |
0 |
T152 |
155893 |
273 |
0 |
0 |
T153 |
13122 |
75 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6413 |
0 |
0 |
T74 |
32446 |
232 |
0 |
0 |
T76 |
63468 |
228 |
0 |
0 |
T104 |
71270 |
489 |
0 |
0 |
T122 |
60975 |
321 |
0 |
0 |
T127 |
4161 |
52 |
0 |
0 |
T129 |
10047 |
84 |
0 |
0 |
T132 |
11145 |
99 |
0 |
0 |
T151 |
19661 |
93 |
0 |
0 |
T152 |
155893 |
266 |
0 |
0 |
T153 |
13122 |
36 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6148 |
0 |
0 |
T74 |
32446 |
194 |
0 |
0 |
T76 |
63468 |
271 |
0 |
0 |
T104 |
71270 |
406 |
0 |
0 |
T122 |
60975 |
232 |
0 |
0 |
T127 |
4161 |
45 |
0 |
0 |
T129 |
10047 |
125 |
0 |
0 |
T132 |
11145 |
113 |
0 |
0 |
T151 |
19661 |
48 |
0 |
0 |
T152 |
155893 |
280 |
0 |
0 |
T153 |
13122 |
45 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6259 |
0 |
0 |
T74 |
32446 |
201 |
0 |
0 |
T76 |
63468 |
327 |
0 |
0 |
T104 |
71270 |
474 |
0 |
0 |
T122 |
60975 |
166 |
0 |
0 |
T127 |
4161 |
5 |
0 |
0 |
T129 |
10047 |
50 |
0 |
0 |
T132 |
11145 |
135 |
0 |
0 |
T151 |
19661 |
22 |
0 |
0 |
T152 |
155893 |
215 |
0 |
0 |
T153 |
13122 |
47 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6303 |
0 |
0 |
T74 |
32446 |
195 |
0 |
0 |
T76 |
63468 |
333 |
0 |
0 |
T104 |
71270 |
615 |
0 |
0 |
T122 |
60975 |
400 |
0 |
0 |
T127 |
4161 |
42 |
0 |
0 |
T129 |
10047 |
54 |
0 |
0 |
T132 |
11145 |
89 |
0 |
0 |
T151 |
19661 |
26 |
0 |
0 |
T152 |
155893 |
231 |
0 |
0 |
T153 |
13122 |
37 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5845 |
0 |
0 |
T74 |
32446 |
204 |
0 |
0 |
T76 |
63468 |
345 |
0 |
0 |
T104 |
71270 |
401 |
0 |
0 |
T122 |
60975 |
364 |
0 |
0 |
T127 |
4161 |
51 |
0 |
0 |
T129 |
10047 |
38 |
0 |
0 |
T132 |
11145 |
102 |
0 |
0 |
T151 |
19661 |
43 |
0 |
0 |
T152 |
155893 |
290 |
0 |
0 |
T153 |
13122 |
46 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5776 |
0 |
0 |
T74 |
32446 |
135 |
0 |
0 |
T76 |
63468 |
302 |
0 |
0 |
T104 |
71270 |
503 |
0 |
0 |
T122 |
60975 |
219 |
0 |
0 |
T127 |
4161 |
8 |
0 |
0 |
T129 |
10047 |
99 |
0 |
0 |
T132 |
11145 |
107 |
0 |
0 |
T151 |
19661 |
44 |
0 |
0 |
T152 |
155893 |
260 |
0 |
0 |
T153 |
13122 |
61 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6836 |
0 |
0 |
T74 |
32446 |
191 |
0 |
0 |
T76 |
63468 |
374 |
0 |
0 |
T104 |
71270 |
566 |
0 |
0 |
T122 |
60975 |
325 |
0 |
0 |
T127 |
4161 |
42 |
0 |
0 |
T129 |
10047 |
154 |
0 |
0 |
T132 |
11145 |
5 |
0 |
0 |
T151 |
19661 |
85 |
0 |
0 |
T152 |
155893 |
289 |
0 |
0 |
T153 |
13122 |
19 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6549 |
0 |
0 |
T74 |
32446 |
203 |
0 |
0 |
T76 |
63468 |
178 |
0 |
0 |
T104 |
71270 |
602 |
0 |
0 |
T122 |
60975 |
251 |
0 |
0 |
T127 |
4161 |
50 |
0 |
0 |
T129 |
10047 |
124 |
0 |
0 |
T132 |
11145 |
116 |
0 |
0 |
T151 |
19661 |
21 |
0 |
0 |
T152 |
155893 |
251 |
0 |
0 |
T153 |
13122 |
63 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6270 |
0 |
0 |
T74 |
32446 |
352 |
0 |
0 |
T76 |
63468 |
421 |
0 |
0 |
T104 |
71270 |
410 |
0 |
0 |
T122 |
60975 |
286 |
0 |
0 |
T123 |
68021 |
491 |
0 |
0 |
T129 |
10047 |
173 |
0 |
0 |
T132 |
11145 |
117 |
0 |
0 |
T151 |
19661 |
62 |
0 |
0 |
T152 |
155893 |
253 |
0 |
0 |
T153 |
13122 |
3 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5961 |
0 |
0 |
T74 |
32446 |
242 |
0 |
0 |
T76 |
63468 |
248 |
0 |
0 |
T104 |
71270 |
383 |
0 |
0 |
T122 |
60975 |
294 |
0 |
0 |
T127 |
4161 |
31 |
0 |
0 |
T129 |
10047 |
14 |
0 |
0 |
T132 |
11145 |
13 |
0 |
0 |
T151 |
19661 |
45 |
0 |
0 |
T152 |
155893 |
275 |
0 |
0 |
T153 |
13122 |
40 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6497 |
0 |
0 |
T74 |
32446 |
275 |
0 |
0 |
T76 |
63468 |
288 |
0 |
0 |
T104 |
71270 |
691 |
0 |
0 |
T122 |
60975 |
346 |
0 |
0 |
T127 |
4161 |
4 |
0 |
0 |
T129 |
10047 |
21 |
0 |
0 |
T132 |
11145 |
119 |
0 |
0 |
T151 |
19661 |
135 |
0 |
0 |
T152 |
155893 |
212 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6260 |
0 |
0 |
T74 |
32446 |
260 |
0 |
0 |
T76 |
63468 |
277 |
0 |
0 |
T104 |
71270 |
302 |
0 |
0 |
T122 |
60975 |
312 |
0 |
0 |
T127 |
4161 |
49 |
0 |
0 |
T129 |
10047 |
55 |
0 |
0 |
T132 |
11145 |
62 |
0 |
0 |
T151 |
19661 |
132 |
0 |
0 |
T152 |
155893 |
237 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5962 |
0 |
0 |
T74 |
32446 |
125 |
0 |
0 |
T76 |
63468 |
278 |
0 |
0 |
T104 |
71270 |
510 |
0 |
0 |
T122 |
60975 |
428 |
0 |
0 |
T127 |
4161 |
2 |
0 |
0 |
T129 |
10047 |
28 |
0 |
0 |
T132 |
11145 |
65 |
0 |
0 |
T151 |
19661 |
37 |
0 |
0 |
T152 |
155893 |
276 |
0 |
0 |
T153 |
13122 |
54 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6052 |
0 |
0 |
T74 |
32446 |
301 |
0 |
0 |
T76 |
63468 |
283 |
0 |
0 |
T104 |
71270 |
414 |
0 |
0 |
T122 |
60975 |
287 |
0 |
0 |
T123 |
68021 |
504 |
0 |
0 |
T129 |
10047 |
43 |
0 |
0 |
T132 |
11145 |
75 |
0 |
0 |
T151 |
19661 |
65 |
0 |
0 |
T152 |
155893 |
229 |
0 |
0 |
T153 |
13122 |
77 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5789 |
0 |
0 |
T74 |
32446 |
269 |
0 |
0 |
T76 |
63468 |
249 |
0 |
0 |
T104 |
71270 |
564 |
0 |
0 |
T122 |
60975 |
279 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
108 |
0 |
0 |
T132 |
11145 |
5 |
0 |
0 |
T151 |
19661 |
62 |
0 |
0 |
T152 |
155893 |
269 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
6146 |
0 |
0 |
T74 |
32446 |
222 |
0 |
0 |
T76 |
63468 |
296 |
0 |
0 |
T104 |
71270 |
564 |
0 |
0 |
T122 |
60975 |
434 |
0 |
0 |
T127 |
4161 |
54 |
0 |
0 |
T129 |
10047 |
56 |
0 |
0 |
T132 |
11145 |
148 |
0 |
0 |
T151 |
19661 |
78 |
0 |
0 |
T152 |
155893 |
266 |
0 |
0 |
T153 |
13122 |
61 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5823 |
0 |
0 |
T74 |
32446 |
253 |
0 |
0 |
T76 |
63468 |
337 |
0 |
0 |
T104 |
71270 |
520 |
0 |
0 |
T122 |
60975 |
259 |
0 |
0 |
T127 |
4161 |
36 |
0 |
0 |
T129 |
10047 |
108 |
0 |
0 |
T132 |
11145 |
68 |
0 |
0 |
T151 |
19661 |
43 |
0 |
0 |
T152 |
155893 |
266 |
0 |
0 |
T153 |
13122 |
9 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2367 |
0 |
0 |
T74 |
32446 |
63 |
0 |
0 |
T76 |
63468 |
38 |
0 |
0 |
T104 |
71270 |
99 |
0 |
0 |
T122 |
60975 |
48 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
19 |
0 |
0 |
T132 |
11145 |
21 |
0 |
0 |
T151 |
19661 |
52 |
0 |
0 |
T152 |
155893 |
262 |
0 |
0 |
T153 |
13122 |
31 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2581 |
0 |
0 |
T74 |
32446 |
83 |
0 |
0 |
T76 |
63468 |
50 |
0 |
0 |
T104 |
71270 |
114 |
0 |
0 |
T122 |
60975 |
86 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
15 |
0 |
0 |
T132 |
11145 |
11 |
0 |
0 |
T151 |
19661 |
46 |
0 |
0 |
T152 |
155893 |
255 |
0 |
0 |
T153 |
13122 |
75 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2646 |
0 |
0 |
T74 |
32446 |
70 |
0 |
0 |
T76 |
63468 |
72 |
0 |
0 |
T104 |
71270 |
136 |
0 |
0 |
T122 |
60975 |
59 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
25 |
0 |
0 |
T132 |
11145 |
18 |
0 |
0 |
T151 |
19661 |
36 |
0 |
0 |
T152 |
155893 |
298 |
0 |
0 |
T153 |
13122 |
52 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2535 |
0 |
0 |
T74 |
32446 |
69 |
0 |
0 |
T76 |
63468 |
38 |
0 |
0 |
T104 |
71270 |
130 |
0 |
0 |
T122 |
60975 |
61 |
0 |
0 |
T127 |
4161 |
2 |
0 |
0 |
T129 |
10047 |
33 |
0 |
0 |
T132 |
11145 |
17 |
0 |
0 |
T151 |
19661 |
38 |
0 |
0 |
T152 |
155893 |
242 |
0 |
0 |
T153 |
13122 |
40 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
3119 |
0 |
0 |
T74 |
32446 |
60 |
0 |
0 |
T76 |
63468 |
105 |
0 |
0 |
T104 |
71270 |
200 |
0 |
0 |
T122 |
60975 |
118 |
0 |
0 |
T123 |
68021 |
160 |
0 |
0 |
T129 |
10047 |
16 |
0 |
0 |
T132 |
11145 |
34 |
0 |
0 |
T151 |
19661 |
52 |
0 |
0 |
T152 |
155893 |
296 |
0 |
0 |
T153 |
13122 |
42 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
5191 |
0 |
0 |
T14 |
479319 |
64 |
0 |
0 |
T21 |
0 |
39 |
0 |
0 |
T23 |
0 |
13 |
0 |
0 |
T24 |
1286 |
0 |
0 |
0 |
T25 |
435612 |
0 |
0 |
0 |
T26 |
164462 |
0 |
0 |
0 |
T27 |
7929 |
0 |
0 |
0 |
T28 |
371404 |
0 |
0 |
0 |
T29 |
120269 |
0 |
0 |
0 |
T30 |
765280 |
0 |
0 |
0 |
T40 |
168281 |
0 |
0 |
0 |
T41 |
33572 |
0 |
0 |
0 |
T154 |
0 |
8 |
0 |
0 |
T155 |
0 |
40 |
0 |
0 |
T156 |
0 |
68 |
0 |
0 |
T157 |
0 |
30 |
0 |
0 |
T158 |
0 |
15 |
0 |
0 |
T159 |
0 |
24 |
0 |
0 |
T160 |
0 |
65 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2412 |
0 |
0 |
T74 |
32446 |
47 |
0 |
0 |
T76 |
63468 |
54 |
0 |
0 |
T104 |
71270 |
85 |
0 |
0 |
T122 |
60975 |
43 |
0 |
0 |
T123 |
68021 |
98 |
0 |
0 |
T129 |
10047 |
22 |
0 |
0 |
T132 |
11145 |
21 |
0 |
0 |
T151 |
19661 |
81 |
0 |
0 |
T152 |
155893 |
251 |
0 |
0 |
T153 |
13122 |
37 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2525 |
0 |
0 |
T74 |
32446 |
57 |
0 |
0 |
T76 |
63468 |
74 |
0 |
0 |
T104 |
71270 |
120 |
0 |
0 |
T122 |
60975 |
46 |
0 |
0 |
T123 |
68021 |
101 |
0 |
0 |
T129 |
10047 |
16 |
0 |
0 |
T132 |
11145 |
23 |
0 |
0 |
T151 |
19661 |
95 |
0 |
0 |
T152 |
155893 |
242 |
0 |
0 |
T153 |
13122 |
32 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2119 |
0 |
0 |
T74 |
32446 |
42 |
0 |
0 |
T76 |
63468 |
52 |
0 |
0 |
T104 |
71270 |
73 |
0 |
0 |
T109 |
16312 |
4 |
0 |
0 |
T127 |
4161 |
6 |
0 |
0 |
T129 |
10047 |
15 |
0 |
0 |
T132 |
11145 |
9 |
0 |
0 |
T151 |
19661 |
43 |
0 |
0 |
T152 |
155893 |
195 |
0 |
0 |
T153 |
13122 |
12 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2232 |
0 |
0 |
T74 |
32446 |
42 |
0 |
0 |
T76 |
63468 |
63 |
0 |
0 |
T104 |
71270 |
65 |
0 |
0 |
T122 |
60975 |
39 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
14 |
0 |
0 |
T132 |
11145 |
20 |
0 |
0 |
T151 |
19661 |
76 |
0 |
0 |
T152 |
155893 |
267 |
0 |
0 |
T153 |
13122 |
56 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2320 |
0 |
0 |
T74 |
32446 |
34 |
0 |
0 |
T76 |
63468 |
47 |
0 |
0 |
T104 |
71270 |
76 |
0 |
0 |
T122 |
60975 |
50 |
0 |
0 |
T127 |
4161 |
6 |
0 |
0 |
T129 |
10047 |
13 |
0 |
0 |
T132 |
11145 |
12 |
0 |
0 |
T151 |
19661 |
67 |
0 |
0 |
T152 |
155893 |
303 |
0 |
0 |
T153 |
13122 |
55 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2285 |
0 |
0 |
T74 |
32446 |
29 |
0 |
0 |
T76 |
63468 |
45 |
0 |
0 |
T104 |
71270 |
67 |
0 |
0 |
T122 |
60975 |
39 |
0 |
0 |
T127 |
4161 |
3 |
0 |
0 |
T129 |
10047 |
10 |
0 |
0 |
T132 |
11145 |
6 |
0 |
0 |
T151 |
19661 |
67 |
0 |
0 |
T152 |
155893 |
266 |
0 |
0 |
T153 |
13122 |
75 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
3270 |
0 |
0 |
T74 |
32446 |
145 |
0 |
0 |
T76 |
63468 |
109 |
0 |
0 |
T104 |
71270 |
230 |
0 |
0 |
T122 |
60975 |
145 |
0 |
0 |
T127 |
4161 |
4 |
0 |
0 |
T129 |
10047 |
40 |
0 |
0 |
T132 |
11145 |
38 |
0 |
0 |
T151 |
19661 |
31 |
0 |
0 |
T152 |
155893 |
295 |
0 |
0 |
T153 |
13122 |
44 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2277 |
0 |
0 |
T74 |
32446 |
38 |
0 |
0 |
T76 |
63468 |
44 |
0 |
0 |
T104 |
71270 |
80 |
0 |
0 |
T122 |
60975 |
41 |
0 |
0 |
T123 |
68021 |
89 |
0 |
0 |
T129 |
10047 |
7 |
0 |
0 |
T132 |
11145 |
9 |
0 |
0 |
T151 |
19661 |
51 |
0 |
0 |
T152 |
155893 |
321 |
0 |
0 |
T153 |
13122 |
35 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
3561 |
0 |
0 |
T74 |
32446 |
106 |
0 |
0 |
T76 |
63468 |
82 |
0 |
0 |
T104 |
71270 |
181 |
0 |
0 |
T122 |
60975 |
140 |
0 |
0 |
T127 |
4161 |
8 |
0 |
0 |
T129 |
10047 |
28 |
0 |
0 |
T132 |
11145 |
38 |
0 |
0 |
T151 |
19661 |
49 |
0 |
0 |
T152 |
155893 |
287 |
0 |
0 |
T153 |
13122 |
68 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2545 |
0 |
0 |
T74 |
32446 |
38 |
0 |
0 |
T76 |
63468 |
59 |
0 |
0 |
T104 |
71270 |
107 |
0 |
0 |
T122 |
60975 |
57 |
0 |
0 |
T127 |
4161 |
6 |
0 |
0 |
T129 |
10047 |
16 |
0 |
0 |
T132 |
11145 |
6 |
0 |
0 |
T151 |
19661 |
87 |
0 |
0 |
T152 |
155893 |
263 |
0 |
0 |
T153 |
13122 |
19 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2375 |
0 |
0 |
T74 |
32446 |
38 |
0 |
0 |
T76 |
63468 |
35 |
0 |
0 |
T104 |
71270 |
88 |
0 |
0 |
T122 |
60975 |
56 |
0 |
0 |
T123 |
68021 |
77 |
0 |
0 |
T129 |
10047 |
13 |
0 |
0 |
T132 |
11145 |
5 |
0 |
0 |
T151 |
19661 |
92 |
0 |
0 |
T152 |
155893 |
291 |
0 |
0 |
T153 |
13122 |
39 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2263 |
0 |
0 |
T74 |
32446 |
52 |
0 |
0 |
T76 |
63468 |
51 |
0 |
0 |
T104 |
71270 |
80 |
0 |
0 |
T122 |
60975 |
41 |
0 |
0 |
T127 |
4161 |
8 |
0 |
0 |
T129 |
10047 |
9 |
0 |
0 |
T132 |
11145 |
9 |
0 |
0 |
T151 |
19661 |
35 |
0 |
0 |
T152 |
155893 |
306 |
0 |
0 |
T153 |
13122 |
21 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2234 |
0 |
0 |
T74 |
32446 |
28 |
0 |
0 |
T76 |
63468 |
32 |
0 |
0 |
T104 |
71270 |
72 |
0 |
0 |
T122 |
60975 |
59 |
0 |
0 |
T123 |
68021 |
79 |
0 |
0 |
T129 |
10047 |
16 |
0 |
0 |
T132 |
11145 |
18 |
0 |
0 |
T151 |
19661 |
59 |
0 |
0 |
T152 |
155893 |
278 |
0 |
0 |
T153 |
13122 |
40 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2119 |
0 |
0 |
T74 |
32446 |
27 |
0 |
0 |
T76 |
63468 |
34 |
0 |
0 |
T104 |
71270 |
47 |
0 |
0 |
T122 |
60975 |
25 |
0 |
0 |
T127 |
4161 |
3 |
0 |
0 |
T129 |
10047 |
5 |
0 |
0 |
T132 |
11145 |
6 |
0 |
0 |
T151 |
19661 |
84 |
0 |
0 |
T152 |
155893 |
234 |
0 |
0 |
T153 |
13122 |
63 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2388 |
0 |
0 |
T74 |
32446 |
43 |
0 |
0 |
T76 |
63468 |
21 |
0 |
0 |
T104 |
71270 |
81 |
0 |
0 |
T122 |
60975 |
38 |
0 |
0 |
T127 |
4161 |
1 |
0 |
0 |
T129 |
10047 |
20 |
0 |
0 |
T132 |
11145 |
7 |
0 |
0 |
T151 |
19661 |
71 |
0 |
0 |
T152 |
155893 |
273 |
0 |
0 |
T153 |
13122 |
39 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
517372001 |
2202 |
0 |
0 |
T74 |
32446 |
48 |
0 |
0 |
T76 |
63468 |
57 |
0 |
0 |
T104 |
71270 |
59 |
0 |
0 |
T122 |
60975 |
28 |
0 |
0 |
T127 |
4161 |
5 |
0 |
0 |
T129 |
10047 |
18 |
0 |
0 |
T132 |
11145 |
8 |
0 |
0 |
T151 |
19661 |
35 |
0 |
0 |
T152 |
155893 |
286 |
0 |
0 |
T153 |
13122 |
38 |
0 |
0 |