Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3268339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4167414

1

T1

2620

T2

1941

T3

2450

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4056561	1			T1	3494		T2	2111		T3	3169
values[0x0]	1688940	1			T1	436		T2	444		T3	462
values[0x1]	1690252	1			T1	449		T2	439		T3	429

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2335399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5100354

1

T1

2943

T2

2166

T3

2795

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27557	1			T2	10		T3	9		T6	253
valid_sources[0x01]	30911	1			T2	9		T3	14		T6	262
valid_sources[0x02]	31605	1			T2	14		T3	26		T6	235
valid_sources[0x03]	26385	1			T2	12		T3	9		T6	244
valid_sources[0x04]	31120	1			T2	12		T3	14		T6	282
valid_sources[0x05]	25796	1			T2	12		T3	18		T6	286
valid_sources[0x06]	27321	1			T2	16		T3	18		T4	1
valid_sources[0x07]	25514	1			T2	17		T3	21		T4	2
valid_sources[0x08]	26720	1			T2	4		T3	17		T4	4
valid_sources[0x09]	27370	1			T2	11		T3	11		T6	229
valid_sources[0x0a]	27967	1			T2	9		T3	12		T6	289
valid_sources[0x0b]	28876	1			T2	5		T3	19		T4	1
valid_sources[0x0c]	28137	1			T2	12		T3	9		T6	248
valid_sources[0x0d]	27974	1			T2	11		T3	14		T6	276
valid_sources[0x0e]	29533	1			T2	9		T3	21		T6	265
valid_sources[0x0f]	26965	1			T2	13		T3	20		T6	278
valid_sources[0x10]	29829	1			T2	11		T3	12		T6	258
valid_sources[0x11]	26299	1			T2	16		T3	10		T6	263
valid_sources[0x12]	27609	1			T2	10		T3	13		T6	242
valid_sources[0x13]	27246	1			T2	7		T3	13		T6	254
valid_sources[0x14]	29485	1			T2	14		T3	18		T6	251
valid_sources[0x15]	27104	1			T2	8		T3	18		T6	297
valid_sources[0x16]	57295	1			T2	16		T3	20		T6	237
valid_sources[0x17]	30144	1			T2	12		T3	10		T6	242
valid_sources[0x18]	27546	1			T2	9		T3	16		T6	240
valid_sources[0x19]	34392	1			T2	10		T3	20		T4	2
valid_sources[0x1a]	58346	1			T2	11		T3	10		T6	279
valid_sources[0x1b]	28306	1			T2	14		T3	17		T6	262
valid_sources[0x1c]	24567	1			T2	19		T3	15		T6	262
valid_sources[0x1d]	29429	1			T2	10		T3	29		T6	246
valid_sources[0x1e]	34894	1			T2	9		T3	11		T6	259
valid_sources[0x1f]	31068	1			T2	12		T3	19		T6	243
valid_sources[0x20]	26914	1			T2	14		T3	8		T6	243
valid_sources[0x21]	29043	1			T2	17		T3	25		T6	241
valid_sources[0x22]	76767	1			T2	12		T3	10		T6	243
valid_sources[0x23]	32462	1			T2	10		T3	5		T6	221
valid_sources[0x24]	29944	1			T2	12		T3	16		T6	271
valid_sources[0x25]	26308	1			T2	6		T3	15		T6	239
valid_sources[0x26]	28049	1			T2	6		T3	14		T6	263
valid_sources[0x27]	28146	1			T2	16		T3	17		T6	235
valid_sources[0x28]	26408	1			T2	14		T3	19		T6	266
valid_sources[0x29]	27131	1			T2	9		T3	15		T6	252
valid_sources[0x2a]	31347	1			T2	7		T3	11		T6	223
valid_sources[0x2b]	32043	1			T2	11		T3	14		T6	269
valid_sources[0x2c]	30935	1			T2	8		T3	25		T6	254
valid_sources[0x2d]	27597	1			T2	8		T3	13		T6	275
valid_sources[0x2e]	25217	1			T2	10		T3	12		T6	252
valid_sources[0x2f]	35608	1			T2	11		T3	21		T6	277
valid_sources[0x30]	29660	1			T2	9		T3	17		T6	211
valid_sources[0x31]	33130	1			T2	6		T3	13		T6	223
valid_sources[0x32]	29016	1			T2	10		T3	24		T6	259
valid_sources[0x33]	27375	1			T2	16		T3	20		T6	266
valid_sources[0x34]	26349	1			T2	9		T3	20		T6	237
valid_sources[0x35]	25961	1			T2	12		T3	21		T6	263
valid_sources[0x36]	28423	1			T2	15		T3	16		T6	248
valid_sources[0x37]	29283	1			T2	13		T3	16		T6	252
valid_sources[0x38]	26013	1			T2	16		T3	14		T6	238
valid_sources[0x39]	26904	1			T2	8		T3	9		T6	267
valid_sources[0x3a]	27741	1			T2	10		T3	14		T6	244
valid_sources[0x3b]	29497	1			T2	7		T3	20		T6	265
valid_sources[0x3c]	29183	1			T2	13		T3	11		T4	3
valid_sources[0x3d]	28597	1			T2	15		T3	11		T6	241
valid_sources[0x3e]	28464	1			T2	9		T3	20		T6	248
valid_sources[0x3f]	26705	1			T2	19		T3	18		T6	256
valid_sources[0x40]	29030	1			T2	7		T3	21		T6	246
valid_sources[0x41]	27971	1			T2	10		T3	17		T6	225
valid_sources[0x42]	30282	1			T2	13		T3	13		T6	234
valid_sources[0x43]	33607	1			T2	14		T3	22		T6	260
valid_sources[0x44]	25995	1			T2	13		T3	14		T6	304
valid_sources[0x45]	25770	1			T2	14		T3	8		T6	265
valid_sources[0x46]	25652	1			T2	14		T3	12		T6	248
valid_sources[0x47]	27649	1			T2	17		T3	11		T6	249
valid_sources[0x48]	26310	1			T2	11		T3	9		T6	261
valid_sources[0x49]	33642	1			T2	6		T3	16		T6	236
valid_sources[0x4a]	26408	1			T2	9		T3	15		T6	263
valid_sources[0x4b]	28813	1			T2	14		T3	8		T6	239
valid_sources[0x4c]	28104	1			T2	12		T3	18		T6	257
valid_sources[0x4d]	32984	1			T2	5		T3	16		T6	258
valid_sources[0x4e]	28385	1			T2	15		T3	23		T6	255
valid_sources[0x4f]	25648	1			T2	8		T3	12		T6	269
valid_sources[0x50]	26489	1			T2	11		T3	16		T6	238
valid_sources[0x51]	32082	1			T2	12		T3	17		T6	254
valid_sources[0x52]	27288	1			T2	13		T3	16		T6	295
valid_sources[0x53]	27424	1			T2	21		T3	11		T6	250
valid_sources[0x54]	26175	1			T2	11		T3	19		T6	264
valid_sources[0x55]	28345	1			T2	8		T3	15		T6	275
valid_sources[0x56]	28623	1			T2	15		T3	19		T6	272
valid_sources[0x57]	29214	1			T2	11		T3	29		T6	247
valid_sources[0x58]	27003	1			T2	18		T3	20		T6	260
valid_sources[0x59]	27674	1			T2	14		T3	8		T6	259
valid_sources[0x5a]	26605	1			T2	12		T3	15		T6	257
valid_sources[0x5b]	35878	1			T2	7		T3	17		T6	252
valid_sources[0x5c]	32129	1			T2	16		T3	18		T6	242
valid_sources[0x5d]	24937	1			T2	7		T3	10		T6	236
valid_sources[0x5e]	28196	1			T2	20		T3	14		T4	2
valid_sources[0x5f]	24515	1			T2	5		T3	17		T6	253
valid_sources[0x60]	26970	1			T2	11		T3	15		T6	222
valid_sources[0x61]	28911	1			T2	16		T3	12		T6	253
valid_sources[0x62]	27069	1			T2	13		T3	18		T6	240
valid_sources[0x63]	27530	1			T2	11		T3	21		T6	269
valid_sources[0x64]	27261	1			T2	8		T3	13		T6	276
valid_sources[0x65]	27121	1			T2	6		T3	14		T6	247
valid_sources[0x66]	28650	1			T2	15		T3	10		T6	237
valid_sources[0x67]	26751	1			T2	12		T3	16		T6	239
valid_sources[0x68]	29299	1			T2	12		T3	16		T6	245
valid_sources[0x69]	32670	1			T2	7		T3	22		T6	250
valid_sources[0x6a]	27081	1			T2	9		T3	14		T6	260
valid_sources[0x6b]	31647	1			T2	11		T3	14		T4	1
valid_sources[0x6c]	30557	1			T2	16		T3	6		T6	251
valid_sources[0x6d]	27007	1			T2	13		T3	11		T6	240
valid_sources[0x6e]	24167	1			T2	8		T3	16		T4	1
valid_sources[0x6f]	27457	1			T2	11		T3	22		T6	241
valid_sources[0x70]	28179	1			T2	16		T3	24		T6	244
valid_sources[0x71]	30849	1			T2	12		T3	12		T6	262
valid_sources[0x72]	26812	1			T2	11		T3	26		T6	278
valid_sources[0x73]	28019	1			T2	13		T3	21		T6	320
valid_sources[0x74]	28503	1			T2	8		T3	17		T6	230
valid_sources[0x75]	31790	1			T2	9		T3	15		T6	280
valid_sources[0x76]	26799	1			T2	13		T3	16		T6	248
valid_sources[0x77]	31292	1			T2	12		T3	5		T6	269
valid_sources[0x78]	32259	1			T2	13		T3	17		T6	248
valid_sources[0x79]	27912	1			T2	16		T3	16		T4	1
valid_sources[0x7a]	28346	1			T2	12		T3	25		T6	269
valid_sources[0x7b]	25034	1			T2	15		T3	12		T6	247
valid_sources[0x7c]	26497	1			T2	17		T3	18		T6	236
valid_sources[0x7d]	26798	1			T2	19		T3	22		T6	263
valid_sources[0x7e]	27484	1			T2	18		T3	15		T6	256
valid_sources[0x7f]	27225	1			T2	19		T3	24		T6	259
valid_sources[0x80]	28775	1			T2	18		T3	17		T6	258

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1087785

1

T1

1740

T2

1064

T3

1571

values[0x0]

all_enables

biggest_size

1550926

1

T1

433

T2

441

T3

457

values[0x1]

all_enables

biggest_size

1528703

1

T1

447

T2

436

T3

422