Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3290133

1

T1

1759

T2

1053

T3

1610

full_word

4168569

1

T1

2620

T2

1941

T3

2450

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7458352	1			T1	4379		T2	2994		T3	4060
auto[TlIntgErrCmd]	133	1			T62	4		T63	5		T64	11
auto[TlIntgErrData]	105	1			T62	8		T63	9		T64	5
auto[TlIntgErrBoth]	112	1			T62	8		T63	6		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4060134

1

T1

3494

T2

2111

T3

3169

auto[1]

3398568

1

T1

885

T2

883

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2971937	1			T1	1754		T2	1047		T3	1598
auto[TlIntgErrNone]	partial	auto[1]	317873	1			T1	5		T2	6		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	1088056	1			T1	1740		T2	1064		T3	1571
auto[TlIntgErrNone]	full_word	auto[1]	3080486	1			T1	880		T2	877		T3	879
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T62	1		T63	1		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T62	2		T63	4		T64	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T64	1		T179	1		T180	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T62	1		T64	2		T117	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T62	3		T63	4		T64	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T62	5		T63	5		T64	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T64	1		T178	1		T179	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T178	1		T177	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T62	3		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T62	5		T63	5		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T64	1		T181	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T106	2		T178	2		T183	1