Unified Coverage Report :: Group :: dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::PutFullData_mask_not_match_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_mask	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_size	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::invalid_a_opcode	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::mask_not_in_enabled_lanes	100.00	1	100	1	64	64
uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::size_over_max	100.00	1	100	1	64	64

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::PutFullData_mask_not_match_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::PutFullData_mask_not_match_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::PutFullData_mask_not_match_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_mask

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_mask

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_size

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::addr_not_align_size

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::invalid_a_opcode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::invalid_a_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::invalid_a_opcode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::mask_not_in_enabled_lanes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::mask_not_in_enabled_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::mask_not_in_enabled_lanes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

---

Group Instance : uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::size_over_max

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::size_over_max

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group Instance uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::size_over_max

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_transitions	2	0	2	100.00	100	1	1	0
cp_value	2	0	2	100.00	100	1	1	2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

4453

1

T103

1

T106

2

T100

7

rising

4454

1

T62

1

T63

1

T103

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16650

1

T62

2

T63

2

T64

7

auto[1]

6299

1

T62

1

T63

1

T103

2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

5056

1

T62

1

T63

1

T64

2

rising

5053

1

T64

2

T103

1

T106

2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15139

1

T62

2

T63

1

T64

5

auto[1]

7810

1

T62

1

T63

2

T64

2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

5056

1

T62

1

T63

1

T64

2

rising

5053

1

T64

2

T103

1

T106

2

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15139

1

T62

2

T63

1

T64

5

auto[1]

7810

1

T62

1

T63

2

T64

2

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

4313

1

T62

1

T63

1

T103

2

rising

4311

1

T62

1

T64

1

T103

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16838

1

T62

2

T63

2

T64

2

auto[1]

6111

1

T62

1

T63

1

T64

5

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

5110

1

T64

1

T106

1

T100

5

rising

5114

1

T106

1

T100

5

T117

1

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15273

1

T62

3

T63

3

T64

6

auto[1]

7676

1

T64

1

T106

1

T100

6

Summary for Variable cp_transitions

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_transitions

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

falling

4554

1

T100

6

T101

7

T102

4

rising

4552

1

T100

7

T101

7

T102

4

---

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16724

1

T62

3

T63

3

T64

7

auto[1]

6225

1

T100

8

T101

9

T102

6