Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T24
1	0	Covered	T4,T6,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T11
1	0	Unreachable
1	1	Covered	T4,T6,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T14,T24

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T24
1	0	Covered	T6,T14,T24

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T14,T24

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T14,T24

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T14
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T14,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	760860548	609323666	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	760860548	3718671	0	0
GntImpliesValid_A	760860548	3718671	0	0
GrantKnown_A	760860548	609323666	0	0
IdxKnown_A	760860548	609323666	0	0
IndexIsCorrect_A	760860548	3718671	0	0
LockArbDecision_A	760860548	0	0	0
NoReadyValidNoGrant_A	760860548	0	0	0
ReadyAndValidImplyGrant_A	760860548	3718671	0	0
ReqAndReadyImplyGrant_A	760860548	3718671	0	0
ReqImpliesValid_A	760860548	3718671	0	0
ReqStaysHighUntilGranted0_M	760860548	0	0	0
RoundRobin_A	760860548	7	0	955
ValidKnown_A	760860548	609323666	0	0
gen_data_port_assertion.DataFlow_A	760860548	3718671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	609323666	0	0
T1	214809	214712	0	0
T2	60477	60415	0	0
T3	77492	77417	0	0
T4	3150	2339	0	0
T5	877	785	0	0
T6	1959524	1131149	0	0
T7	446336	401914	0	0
T8	206835	125297	0	0
T9	15699	13734	0	0
T10	3257	3075	0	0
T11	576	288	0	0
T12	2160	2160	0	0
T14	570725	564480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	609323666	0	0
T1	214809	214712	0	0
T2	60477	60415	0	0
T3	77492	77417	0	0
T4	3150	2339	0	0
T5	877	785	0	0
T6	1959524	1131149	0	0
T7	446336	401914	0	0
T8	206835	125297	0	0
T9	15699	13734	0	0
T10	3257	3075	0	0
T11	576	288	0	0
T12	2160	2160	0	0
T14	570725	564480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	609323666	0	0
T1	214809	214712	0	0
T2	60477	60415	0	0
T3	77492	77417	0	0
T4	3150	2339	0	0
T5	877	785	0	0
T6	1959524	1131149	0	0
T7	446336	401914	0	0
T8	206835	125297	0	0
T9	15699	13734	0	0
T10	3257	3075	0	0
T11	576	288	0	0
T12	2160	2160	0	0
T14	570725	564480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	7	0	955
T6	326512	1	0	1
T7	357600	0	0	1
T8	43891	0	0	1
T9	12647	0	0	1
T10	3069	0	0	1
T11	2234	0	0	1
T12	9092	0	0	1
T13	5186	0	0	1
T14	119855	0	0	1
T23	869384	0	0	1
T27	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	609323666	0	0
T1	214809	214712	0	0
T2	60477	60415	0	0
T3	77492	77417	0	0
T4	3150	2339	0	0
T5	877	785	0	0
T6	1959524	1131149	0	0
T7	446336	401914	0	0
T8	206835	125297	0	0
T9	15699	13734	0	0
T10	3257	3075	0	0
T11	576	288	0	0
T12	2160	2160	0	0
T14	570725	564480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760860548	3718671	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	2414	32	0	0
T5	877	0	0	0
T6	1959524	28319	0	0
T7	446336	832	0	0
T8	206835	832	0	0
T9	15699	832	0	0
T10	3257	832	0	0
T11	576	0	0	0
T12	4320	832	0	0
T14	1141450	6057	0	0
T15	0	7867	0	0
T23	254974	0	0	0
T24	0	12087	0	0
T25	0	2840	0	0
T27	0	1768	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T36	0	6112	0	0
T37	0	8088	0	0
T42	0	892	0	0
T46	4960	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T24
1	0	Covered	T4,T6,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T11
1	0	Unreachable
1	1	Covered	T4,T6,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T14
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150113622	26353239	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	150113622	605027	0	0
GntImpliesValid_A	150113622	605027	0	0
GrantKnown_A	150113622	26353239	0	0
IdxKnown_A	150113622	26353239	0	0
IndexIsCorrect_A	150113622	605027	0	0
LockArbDecision_A	150113622	0	0	0
NoReadyValidNoGrant_A	150113622	0	0	0
ReadyAndValidImplyGrant_A	150113622	605027	0	0
ReqAndReadyImplyGrant_A	150113622	605027	0	0
ReqImpliesValid_A	150113622	605027	0	0
ReqStaysHighUntilGranted0_M	150113622	0	0	0
RoundRobin_A	150113622	0	0	0
ValidKnown_A	150113622	26353239	0	0
gen_data_port_assertion.DataFlow_A	150113622	605027	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	26353239	0	0
T4	736	736	0	0
T6	816506	111336	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	288	0	0
T12	2160	0	0	0
T14	570725	82480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	26353239	0	0
T4	736	736	0	0
T6	816506	111336	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	288	0	0
T12	2160	0	0	0
T14	570725	82480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	26353239	0	0
T4	736	736	0	0
T6	816506	111336	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	288	0	0
T12	2160	0	0	0
T14	570725	82480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	26353239	0	0
T4	736	736	0	0
T6	816506	111336	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	288	0	0
T12	2160	0	0	0
T14	570725	82480	0	0
T23	127487	121664	0	0
T24	0	147768	0	0
T25	0	232392	0	0
T27	0	36888	0	0
T28	0	29472	0	0
T29	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	605027	0	0
T4	736	16	0	0
T6	816506	4164	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	2720	0	0
T23	127487	0	0	0
T24	0	6606	0	0
T25	0	2840	0	0
T27	0	1709	0	0
T28	0	240	0	0
T34	0	243	0	0
T35	0	92	0	0
T37	0	240	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T14,T24

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T14,T24
1	0	Covered	T6,T14,T24

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T6,T14,T24

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T14,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T14,T24
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T14,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T14,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150113622	122426948	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	150113622	840260	0	0
GntImpliesValid_A	150113622	840260	0	0
GrantKnown_A	150113622	122426948	0	0
IdxKnown_A	150113622	122426948	0	0
IndexIsCorrect_A	150113622	840260	0	0
LockArbDecision_A	150113622	0	0	0
NoReadyValidNoGrant_A	150113622	0	0	0
ReadyAndValidImplyGrant_A	150113622	840260	0	0
ReqAndReadyImplyGrant_A	150113622	840260	0	0
ReqImpliesValid_A	150113622	840260	0	0
ReqStaysHighUntilGranted0_M	150113622	0	0	0
RoundRobin_A	150113622	0	0	0
ValidKnown_A	150113622	122426948	0	0
gen_data_port_assertion.DataFlow_A	150113622	840260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	122426948	0	0
T1	51376	51376	0	0
T2	11504	11504	0	0
T3	18611	18611	0	0
T4	736	0	0	0
T6	816506	693323	0	0
T7	44368	44368	0	0
T8	81472	81472	0	0
T9	1526	1184	0	0
T10	94	94	0	0
T11	288	0	0	0
T12	0	2160	0	0
T14	0	482000	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	122426948	0	0
T1	51376	51376	0	0
T2	11504	11504	0	0
T3	18611	18611	0	0
T4	736	0	0	0
T6	816506	693323	0	0
T7	44368	44368	0	0
T8	81472	81472	0	0
T9	1526	1184	0	0
T10	94	94	0	0
T11	288	0	0	0
T12	0	2160	0	0
T14	0	482000	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	122426948	0	0
T1	51376	51376	0	0
T2	11504	11504	0	0
T3	18611	18611	0	0
T4	736	0	0	0
T6	816506	693323	0	0
T7	44368	44368	0	0
T8	81472	81472	0	0
T9	1526	1184	0	0
T10	94	94	0	0
T11	288	0	0	0
T12	0	2160	0	0
T14	0	482000	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	122426948	0	0
T1	51376	51376	0	0
T2	11504	11504	0	0
T3	18611	18611	0	0
T4	736	0	0	0
T6	816506	693323	0	0
T7	44368	44368	0	0
T8	81472	81472	0	0
T9	1526	1184	0	0
T10	94	94	0	0
T11	288	0	0	0
T12	0	2160	0	0
T14	0	482000	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150113622	840260	0	0
T6	816506	4802	0	0
T7	44368	0	0	0
T8	81472	0	0	0
T9	1526	0	0	0
T10	94	0	0	0
T11	288	0	0	0
T12	2160	0	0	0
T14	570725	3337	0	0
T15	0	7867	0	0
T23	127487	0	0	0
T24	0	5481	0	0
T27	0	59	0	0
T36	0	6112	0	0
T37	0	7848	0	0
T38	0	355	0	0
T42	0	892	0	0
T46	4960	0	0	0
T58	0	10312	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T14,T24

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T14
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T14,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	460633304	460543479	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	460633304	2273384	0	0
GntImpliesValid_A	460633304	2273384	0	0
GrantKnown_A	460633304	460543479	0	0
IdxKnown_A	460633304	460543479	0	0
IndexIsCorrect_A	460633304	2273384	0	0
LockArbDecision_A	460633304	0	0	0
NoReadyValidNoGrant_A	460633304	0	0	0
ReadyAndValidImplyGrant_A	460633304	2273384	0	0
ReqAndReadyImplyGrant_A	460633304	2273384	0	0
ReqImpliesValid_A	460633304	2273384	0	0
ReqStaysHighUntilGranted0_M	460633304	0	0	0
RoundRobin_A	460633304	7	0	955
ValidKnown_A	460633304	460543479	0	0
gen_data_port_assertion.DataFlow_A	460633304	2273384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	460543479	0	0
T1	163433	163336	0	0
T2	48973	48911	0	0
T3	58881	58806	0	0
T4	1678	1603	0	0
T5	877	785	0	0
T6	326512	326490	0	0
T7	357600	357546	0	0
T8	43891	43825	0	0
T9	12647	12550	0	0
T10	3069	2981	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	460543479	0	0
T1	163433	163336	0	0
T2	48973	48911	0	0
T3	58881	58806	0	0
T4	1678	1603	0	0
T5	877	785	0	0
T6	326512	326490	0	0
T7	357600	357546	0	0
T8	43891	43825	0	0
T9	12647	12550	0	0
T10	3069	2981	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	460543479	0	0
T1	163433	163336	0	0
T2	48973	48911	0	0
T3	58881	58806	0	0
T4	1678	1603	0	0
T5	877	785	0	0
T6	326512	326490	0	0
T7	357600	357546	0	0
T8	43891	43825	0	0
T9	12647	12550	0	0
T10	3069	2981	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	7	0	955
T6	326512	1	0	1
T7	357600	0	0	1
T8	43891	0	0	1
T9	12647	0	0	1
T10	3069	0	0	1
T11	2234	0	0	1
T12	9092	0	0	1
T13	5186	0	0	1
T14	119855	0	0	1
T23	869384	0	0	1
T27	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	460543479	0	0
T1	163433	163336	0	0
T2	48973	48911	0	0
T3	58881	58806	0	0
T4	1678	1603	0	0
T5	877	785	0	0
T6	326512	326490	0	0
T7	357600	357546	0	0
T8	43891	43825	0	0
T9	12647	12550	0	0
T10	3069	2981	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460633304	2273384	0	0
T1	163433	832	0	0
T2	48973	832	0	0
T3	58881	832	0	0
T4	1678	16	0	0
T5	877	0	0	0
T6	326512	19353	0	0
T7	357600	832	0	0
T8	43891	832	0	0
T9	12647	832	0	0
T10	3069	832	0	0
T12	0	832	0	0