Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3502 |
0 |
0 |
T62 |
19659 |
2 |
0 |
0 |
T63 |
69700 |
3 |
0 |
0 |
T64 |
20010 |
4 |
0 |
0 |
T100 |
3732 |
11 |
0 |
0 |
T101 |
12590 |
3 |
0 |
0 |
T102 |
9412 |
5 |
0 |
0 |
T103 |
28982 |
2 |
0 |
0 |
T106 |
66700 |
1 |
0 |
0 |
T117 |
62573 |
3 |
0 |
0 |
T161 |
26726 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1398 |
0 |
0 |
T63 |
69700 |
68 |
0 |
0 |
T102 |
9412 |
12 |
0 |
0 |
T106 |
66700 |
83 |
0 |
0 |
T113 |
16343 |
5 |
0 |
0 |
T117 |
62573 |
33 |
0 |
0 |
T125 |
6914 |
2 |
0 |
0 |
T152 |
7318 |
13 |
0 |
0 |
T154 |
12726 |
23 |
0 |
0 |
T162 |
5735 |
4 |
0 |
0 |
T163 |
10167 |
17 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1528 |
0 |
0 |
T63 |
69700 |
80 |
0 |
0 |
T102 |
9412 |
15 |
0 |
0 |
T106 |
66700 |
61 |
0 |
0 |
T109 |
17816 |
2 |
0 |
0 |
T117 |
62573 |
57 |
0 |
0 |
T121 |
4069 |
6 |
0 |
0 |
T125 |
6914 |
10 |
0 |
0 |
T152 |
7318 |
33 |
0 |
0 |
T154 |
12726 |
55 |
0 |
0 |
T162 |
5735 |
13 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1771 |
0 |
0 |
T63 |
69700 |
189 |
0 |
0 |
T102 |
9412 |
10 |
0 |
0 |
T106 |
66700 |
136 |
0 |
0 |
T117 |
62573 |
103 |
0 |
0 |
T125 |
6914 |
2 |
0 |
0 |
T152 |
7318 |
46 |
0 |
0 |
T154 |
12726 |
49 |
0 |
0 |
T162 |
5735 |
6 |
0 |
0 |
T163 |
10167 |
29 |
0 |
0 |
T164 |
6680 |
9 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5902 |
0 |
0 |
T63 |
69700 |
1407 |
0 |
0 |
T102 |
9412 |
103 |
0 |
0 |
T106 |
66700 |
1123 |
0 |
0 |
T117 |
62573 |
674 |
0 |
0 |
T121 |
4069 |
68 |
0 |
0 |
T125 |
6914 |
66 |
0 |
0 |
T152 |
7318 |
45 |
0 |
0 |
T154 |
12726 |
40 |
0 |
0 |
T162 |
5735 |
6 |
0 |
0 |
T163 |
10167 |
181 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5493 |
0 |
0 |
T63 |
69700 |
1481 |
0 |
0 |
T102 |
9412 |
24 |
0 |
0 |
T106 |
66700 |
1097 |
0 |
0 |
T117 |
62573 |
450 |
0 |
0 |
T121 |
4069 |
51 |
0 |
0 |
T125 |
6914 |
63 |
0 |
0 |
T152 |
7318 |
23 |
0 |
0 |
T154 |
12726 |
30 |
0 |
0 |
T162 |
5735 |
5 |
0 |
0 |
T163 |
10167 |
14 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
6130 |
0 |
0 |
T63 |
69700 |
1325 |
0 |
0 |
T102 |
9412 |
112 |
0 |
0 |
T106 |
66700 |
1461 |
0 |
0 |
T117 |
62573 |
592 |
0 |
0 |
T121 |
4069 |
60 |
0 |
0 |
T125 |
6914 |
96 |
0 |
0 |
T152 |
7318 |
5 |
0 |
0 |
T154 |
12726 |
34 |
0 |
0 |
T162 |
5735 |
119 |
0 |
0 |
T163 |
10167 |
157 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5737 |
0 |
0 |
T63 |
69700 |
1222 |
0 |
0 |
T102 |
9412 |
122 |
0 |
0 |
T106 |
66700 |
1001 |
0 |
0 |
T109 |
17816 |
1 |
0 |
0 |
T117 |
62573 |
702 |
0 |
0 |
T121 |
4069 |
54 |
0 |
0 |
T125 |
6914 |
128 |
0 |
0 |
T152 |
7318 |
15 |
0 |
0 |
T154 |
12726 |
61 |
0 |
0 |
T162 |
5735 |
115 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5162 |
0 |
0 |
T63 |
69700 |
958 |
0 |
0 |
T102 |
9412 |
249 |
0 |
0 |
T106 |
66700 |
1178 |
0 |
0 |
T113 |
16343 |
2 |
0 |
0 |
T117 |
62573 |
627 |
0 |
0 |
T121 |
4069 |
75 |
0 |
0 |
T125 |
6914 |
9 |
0 |
0 |
T152 |
7318 |
12 |
0 |
0 |
T154 |
12726 |
26 |
0 |
0 |
T162 |
5735 |
135 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5484 |
0 |
0 |
T63 |
69700 |
983 |
0 |
0 |
T102 |
9412 |
113 |
0 |
0 |
T106 |
66700 |
1823 |
0 |
0 |
T117 |
62573 |
546 |
0 |
0 |
T121 |
4069 |
1 |
0 |
0 |
T125 |
6914 |
4 |
0 |
0 |
T152 |
7318 |
32 |
0 |
0 |
T154 |
12726 |
13 |
0 |
0 |
T162 |
5735 |
14 |
0 |
0 |
T163 |
10167 |
149 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
6160 |
0 |
0 |
T63 |
69700 |
1547 |
0 |
0 |
T102 |
9412 |
22 |
0 |
0 |
T106 |
66700 |
1617 |
0 |
0 |
T117 |
62573 |
850 |
0 |
0 |
T121 |
4069 |
10 |
0 |
0 |
T125 |
6914 |
81 |
0 |
0 |
T152 |
7318 |
22 |
0 |
0 |
T154 |
12726 |
24 |
0 |
0 |
T162 |
5735 |
9 |
0 |
0 |
T163 |
10167 |
22 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
5301 |
0 |
0 |
T63 |
69700 |
1372 |
0 |
0 |
T102 |
9412 |
15 |
0 |
0 |
T106 |
66700 |
731 |
0 |
0 |
T113 |
16343 |
6 |
0 |
0 |
T117 |
62573 |
533 |
0 |
0 |
T125 |
6914 |
141 |
0 |
0 |
T152 |
7318 |
11 |
0 |
0 |
T154 |
12726 |
16 |
0 |
0 |
T162 |
5735 |
143 |
0 |
0 |
T163 |
10167 |
164 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3359 |
0 |
0 |
T63 |
69700 |
612 |
0 |
0 |
T102 |
9412 |
65 |
0 |
0 |
T106 |
66700 |
492 |
0 |
0 |
T117 |
62573 |
386 |
0 |
0 |
T121 |
4069 |
8 |
0 |
0 |
T125 |
6914 |
36 |
0 |
0 |
T152 |
7318 |
18 |
0 |
0 |
T154 |
12726 |
67 |
0 |
0 |
T162 |
5735 |
10 |
0 |
0 |
T163 |
10167 |
126 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2967 |
0 |
0 |
T63 |
69700 |
426 |
0 |
0 |
T102 |
9412 |
14 |
0 |
0 |
T106 |
66700 |
567 |
0 |
0 |
T117 |
62573 |
292 |
0 |
0 |
T125 |
6914 |
15 |
0 |
0 |
T152 |
7318 |
12 |
0 |
0 |
T154 |
12726 |
45 |
0 |
0 |
T162 |
5735 |
7 |
0 |
0 |
T163 |
10167 |
21 |
0 |
0 |
T164 |
6680 |
55 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3222 |
0 |
0 |
T63 |
69700 |
494 |
0 |
0 |
T102 |
9412 |
9 |
0 |
0 |
T106 |
66700 |
648 |
0 |
0 |
T108 |
6554 |
3 |
0 |
0 |
T117 |
62573 |
201 |
0 |
0 |
T121 |
4069 |
13 |
0 |
0 |
T125 |
6914 |
53 |
0 |
0 |
T152 |
7318 |
29 |
0 |
0 |
T154 |
12726 |
86 |
0 |
0 |
T162 |
5735 |
54 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2698 |
0 |
0 |
T63 |
69700 |
441 |
0 |
0 |
T102 |
9412 |
96 |
0 |
0 |
T106 |
66700 |
390 |
0 |
0 |
T117 |
62573 |
199 |
0 |
0 |
T125 |
6914 |
3 |
0 |
0 |
T152 |
7318 |
33 |
0 |
0 |
T154 |
12726 |
35 |
0 |
0 |
T162 |
5735 |
8 |
0 |
0 |
T163 |
10167 |
77 |
0 |
0 |
T164 |
6680 |
6 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3500 |
0 |
0 |
T63 |
69700 |
608 |
0 |
0 |
T102 |
9412 |
37 |
0 |
0 |
T106 |
66700 |
645 |
0 |
0 |
T108 |
6554 |
1 |
0 |
0 |
T117 |
62573 |
354 |
0 |
0 |
T125 |
6914 |
33 |
0 |
0 |
T154 |
12726 |
12 |
0 |
0 |
T162 |
5735 |
67 |
0 |
0 |
T163 |
10167 |
55 |
0 |
0 |
T165 |
6533 |
6 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3128 |
0 |
0 |
T63 |
69700 |
834 |
0 |
0 |
T102 |
9412 |
53 |
0 |
0 |
T106 |
66700 |
541 |
0 |
0 |
T117 |
62573 |
167 |
0 |
0 |
T121 |
4069 |
17 |
0 |
0 |
T125 |
6914 |
5 |
0 |
0 |
T152 |
7318 |
31 |
0 |
0 |
T154 |
12726 |
50 |
0 |
0 |
T162 |
5735 |
65 |
0 |
0 |
T163 |
10167 |
61 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2833 |
0 |
0 |
T63 |
69700 |
379 |
0 |
0 |
T102 |
9412 |
62 |
0 |
0 |
T106 |
66700 |
440 |
0 |
0 |
T117 |
62573 |
253 |
0 |
0 |
T121 |
4069 |
14 |
0 |
0 |
T125 |
6914 |
32 |
0 |
0 |
T152 |
7318 |
53 |
0 |
0 |
T154 |
12726 |
39 |
0 |
0 |
T162 |
5735 |
9 |
0 |
0 |
T163 |
10167 |
63 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2917 |
0 |
0 |
T63 |
69700 |
401 |
0 |
0 |
T102 |
9412 |
55 |
0 |
0 |
T106 |
66700 |
712 |
0 |
0 |
T117 |
62573 |
296 |
0 |
0 |
T125 |
6914 |
18 |
0 |
0 |
T152 |
7318 |
27 |
0 |
0 |
T154 |
12726 |
11 |
0 |
0 |
T162 |
5735 |
6 |
0 |
0 |
T163 |
10167 |
91 |
0 |
0 |
T164 |
6680 |
27 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3040 |
0 |
0 |
T63 |
69700 |
420 |
0 |
0 |
T102 |
9412 |
54 |
0 |
0 |
T106 |
66700 |
558 |
0 |
0 |
T117 |
62573 |
183 |
0 |
0 |
T121 |
4069 |
1 |
0 |
0 |
T125 |
6914 |
21 |
0 |
0 |
T152 |
7318 |
30 |
0 |
0 |
T154 |
12726 |
85 |
0 |
0 |
T162 |
5735 |
4 |
0 |
0 |
T163 |
10167 |
62 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3172 |
0 |
0 |
T63 |
69700 |
512 |
0 |
0 |
T102 |
9412 |
93 |
0 |
0 |
T106 |
66700 |
608 |
0 |
0 |
T117 |
62573 |
297 |
0 |
0 |
T121 |
4069 |
4 |
0 |
0 |
T125 |
6914 |
23 |
0 |
0 |
T152 |
7318 |
6 |
0 |
0 |
T154 |
12726 |
25 |
0 |
0 |
T162 |
5735 |
5 |
0 |
0 |
T163 |
10167 |
69 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2957 |
0 |
0 |
T63 |
69700 |
464 |
0 |
0 |
T102 |
9412 |
7 |
0 |
0 |
T106 |
66700 |
500 |
0 |
0 |
T117 |
62573 |
267 |
0 |
0 |
T125 |
6914 |
34 |
0 |
0 |
T152 |
7318 |
17 |
0 |
0 |
T154 |
12726 |
31 |
0 |
0 |
T162 |
5735 |
58 |
0 |
0 |
T163 |
10167 |
121 |
0 |
0 |
T164 |
6680 |
19 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3053 |
0 |
0 |
T63 |
69700 |
500 |
0 |
0 |
T102 |
9412 |
71 |
0 |
0 |
T106 |
66700 |
538 |
0 |
0 |
T117 |
62573 |
339 |
0 |
0 |
T121 |
4069 |
31 |
0 |
0 |
T125 |
6914 |
7 |
0 |
0 |
T152 |
7318 |
21 |
0 |
0 |
T154 |
12726 |
49 |
0 |
0 |
T162 |
5735 |
4 |
0 |
0 |
T163 |
10167 |
76 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3108 |
0 |
0 |
T63 |
69700 |
445 |
0 |
0 |
T102 |
9412 |
94 |
0 |
0 |
T106 |
66700 |
506 |
0 |
0 |
T117 |
62573 |
262 |
0 |
0 |
T121 |
4069 |
33 |
0 |
0 |
T125 |
6914 |
53 |
0 |
0 |
T152 |
7318 |
32 |
0 |
0 |
T154 |
12726 |
15 |
0 |
0 |
T162 |
5735 |
38 |
0 |
0 |
T163 |
10167 |
55 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2571 |
0 |
0 |
T63 |
69700 |
492 |
0 |
0 |
T102 |
9412 |
53 |
0 |
0 |
T106 |
66700 |
358 |
0 |
0 |
T117 |
62573 |
138 |
0 |
0 |
T121 |
4069 |
32 |
0 |
0 |
T125 |
6914 |
46 |
0 |
0 |
T152 |
7318 |
47 |
0 |
0 |
T154 |
12726 |
35 |
0 |
0 |
T162 |
5735 |
48 |
0 |
0 |
T163 |
10167 |
23 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3102 |
0 |
0 |
T63 |
69700 |
428 |
0 |
0 |
T102 |
9412 |
98 |
0 |
0 |
T106 |
66700 |
374 |
0 |
0 |
T117 |
62573 |
349 |
0 |
0 |
T125 |
6914 |
55 |
0 |
0 |
T152 |
7318 |
24 |
0 |
0 |
T154 |
12726 |
64 |
0 |
0 |
T162 |
5735 |
8 |
0 |
0 |
T163 |
10167 |
112 |
0 |
0 |
T164 |
6680 |
38 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3187 |
0 |
0 |
T63 |
69700 |
512 |
0 |
0 |
T102 |
9412 |
69 |
0 |
0 |
T106 |
66700 |
574 |
0 |
0 |
T117 |
62573 |
218 |
0 |
0 |
T152 |
7318 |
41 |
0 |
0 |
T154 |
12726 |
20 |
0 |
0 |
T162 |
5735 |
56 |
0 |
0 |
T163 |
10167 |
57 |
0 |
0 |
T164 |
6680 |
35 |
0 |
0 |
T165 |
6533 |
4 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3293 |
0 |
0 |
T63 |
69700 |
557 |
0 |
0 |
T102 |
9412 |
9 |
0 |
0 |
T106 |
66700 |
415 |
0 |
0 |
T117 |
62573 |
470 |
0 |
0 |
T125 |
6914 |
31 |
0 |
0 |
T152 |
7318 |
9 |
0 |
0 |
T154 |
12726 |
28 |
0 |
0 |
T162 |
5735 |
59 |
0 |
0 |
T163 |
10167 |
110 |
0 |
0 |
T164 |
6680 |
36 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3431 |
0 |
0 |
T63 |
69700 |
782 |
0 |
0 |
T102 |
9412 |
63 |
0 |
0 |
T106 |
66700 |
652 |
0 |
0 |
T117 |
62573 |
230 |
0 |
0 |
T125 |
6914 |
15 |
0 |
0 |
T152 |
7318 |
16 |
0 |
0 |
T154 |
12726 |
33 |
0 |
0 |
T162 |
5735 |
6 |
0 |
0 |
T163 |
10167 |
125 |
0 |
0 |
T164 |
6680 |
54 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3053 |
0 |
0 |
T63 |
69700 |
445 |
0 |
0 |
T102 |
9412 |
75 |
0 |
0 |
T106 |
66700 |
605 |
0 |
0 |
T117 |
62573 |
235 |
0 |
0 |
T121 |
4069 |
34 |
0 |
0 |
T125 |
6914 |
6 |
0 |
0 |
T152 |
7318 |
42 |
0 |
0 |
T154 |
12726 |
17 |
0 |
0 |
T162 |
5735 |
8 |
0 |
0 |
T163 |
10167 |
49 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3308 |
0 |
0 |
T63 |
69700 |
589 |
0 |
0 |
T102 |
9412 |
131 |
0 |
0 |
T106 |
66700 |
502 |
0 |
0 |
T117 |
62573 |
288 |
0 |
0 |
T121 |
4069 |
1 |
0 |
0 |
T125 |
6914 |
39 |
0 |
0 |
T152 |
7318 |
15 |
0 |
0 |
T154 |
12726 |
18 |
0 |
0 |
T162 |
5735 |
54 |
0 |
0 |
T163 |
10167 |
70 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3156 |
0 |
0 |
T63 |
69700 |
643 |
0 |
0 |
T102 |
9412 |
49 |
0 |
0 |
T106 |
66700 |
612 |
0 |
0 |
T117 |
62573 |
179 |
0 |
0 |
T121 |
4069 |
23 |
0 |
0 |
T125 |
6914 |
34 |
0 |
0 |
T152 |
7318 |
13 |
0 |
0 |
T154 |
12726 |
30 |
0 |
0 |
T162 |
5735 |
64 |
0 |
0 |
T163 |
10167 |
16 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2640 |
0 |
0 |
T63 |
69700 |
472 |
0 |
0 |
T102 |
9412 |
56 |
0 |
0 |
T106 |
66700 |
274 |
0 |
0 |
T117 |
62573 |
391 |
0 |
0 |
T121 |
4069 |
15 |
0 |
0 |
T125 |
6914 |
33 |
0 |
0 |
T152 |
7318 |
5 |
0 |
0 |
T154 |
12726 |
33 |
0 |
0 |
T162 |
5735 |
10 |
0 |
0 |
T163 |
10167 |
45 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3184 |
0 |
0 |
T63 |
69700 |
493 |
0 |
0 |
T102 |
9412 |
12 |
0 |
0 |
T106 |
66700 |
472 |
0 |
0 |
T117 |
62573 |
368 |
0 |
0 |
T121 |
4069 |
49 |
0 |
0 |
T125 |
6914 |
58 |
0 |
0 |
T152 |
7318 |
1 |
0 |
0 |
T154 |
12726 |
42 |
0 |
0 |
T162 |
5735 |
7 |
0 |
0 |
T163 |
10167 |
85 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
3049 |
0 |
0 |
T63 |
69700 |
423 |
0 |
0 |
T102 |
9412 |
91 |
0 |
0 |
T106 |
66700 |
653 |
0 |
0 |
T117 |
62573 |
301 |
0 |
0 |
T121 |
4069 |
21 |
0 |
0 |
T125 |
6914 |
47 |
0 |
0 |
T154 |
12726 |
22 |
0 |
0 |
T162 |
5735 |
14 |
0 |
0 |
T163 |
10167 |
56 |
0 |
0 |
T164 |
6680 |
29 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1619 |
0 |
0 |
T63 |
69700 |
112 |
0 |
0 |
T102 |
9412 |
15 |
0 |
0 |
T106 |
66700 |
120 |
0 |
0 |
T117 |
62573 |
47 |
0 |
0 |
T121 |
4069 |
4 |
0 |
0 |
T152 |
7318 |
21 |
0 |
0 |
T154 |
12726 |
37 |
0 |
0 |
T162 |
5735 |
11 |
0 |
0 |
T163 |
10167 |
19 |
0 |
0 |
T164 |
6680 |
8 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1633 |
0 |
0 |
T63 |
69700 |
114 |
0 |
0 |
T102 |
9412 |
27 |
0 |
0 |
T106 |
66700 |
114 |
0 |
0 |
T113 |
16343 |
2 |
0 |
0 |
T117 |
62573 |
74 |
0 |
0 |
T121 |
4069 |
9 |
0 |
0 |
T125 |
6914 |
8 |
0 |
0 |
T154 |
12726 |
93 |
0 |
0 |
T162 |
5735 |
8 |
0 |
0 |
T163 |
10167 |
8 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1525 |
0 |
0 |
T63 |
69700 |
113 |
0 |
0 |
T102 |
9412 |
21 |
0 |
0 |
T106 |
66700 |
96 |
0 |
0 |
T117 |
62573 |
67 |
0 |
0 |
T121 |
4069 |
3 |
0 |
0 |
T125 |
6914 |
10 |
0 |
0 |
T152 |
7318 |
3 |
0 |
0 |
T154 |
12726 |
77 |
0 |
0 |
T162 |
5735 |
11 |
0 |
0 |
T163 |
10167 |
29 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1585 |
0 |
0 |
T63 |
69700 |
105 |
0 |
0 |
T102 |
9412 |
12 |
0 |
0 |
T106 |
66700 |
127 |
0 |
0 |
T117 |
62573 |
55 |
0 |
0 |
T121 |
4069 |
7 |
0 |
0 |
T125 |
6914 |
14 |
0 |
0 |
T152 |
7318 |
18 |
0 |
0 |
T154 |
12726 |
50 |
0 |
0 |
T162 |
5735 |
14 |
0 |
0 |
T163 |
10167 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1876 |
0 |
0 |
T63 |
69700 |
210 |
0 |
0 |
T102 |
9412 |
8 |
0 |
0 |
T106 |
66700 |
191 |
0 |
0 |
T117 |
62573 |
114 |
0 |
0 |
T121 |
4069 |
6 |
0 |
0 |
T125 |
6914 |
8 |
0 |
0 |
T152 |
7318 |
13 |
0 |
0 |
T154 |
12726 |
58 |
0 |
0 |
T162 |
5735 |
6 |
0 |
0 |
T163 |
10167 |
39 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2882 |
0 |
0 |
T15 |
269403 |
42 |
0 |
0 |
T19 |
0 |
25 |
0 |
0 |
T20 |
0 |
10 |
0 |
0 |
T21 |
0 |
33 |
0 |
0 |
T38 |
259348 |
0 |
0 |
0 |
T40 |
7703 |
0 |
0 |
0 |
T42 |
467197 |
0 |
0 |
0 |
T48 |
29613 |
0 |
0 |
0 |
T61 |
990 |
0 |
0 |
0 |
T82 |
0 |
22 |
0 |
0 |
T90 |
2395 |
0 |
0 |
0 |
T155 |
71199 |
0 |
0 |
0 |
T166 |
0 |
35 |
0 |
0 |
T167 |
0 |
6 |
0 |
0 |
T168 |
0 |
28 |
0 |
0 |
T169 |
0 |
15 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
T171 |
53664 |
0 |
0 |
0 |
T172 |
271306 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1540 |
0 |
0 |
T63 |
69700 |
95 |
0 |
0 |
T102 |
9412 |
3 |
0 |
0 |
T106 |
66700 |
139 |
0 |
0 |
T117 |
62573 |
73 |
0 |
0 |
T121 |
4069 |
4 |
0 |
0 |
T152 |
7318 |
35 |
0 |
0 |
T154 |
12726 |
16 |
0 |
0 |
T162 |
5735 |
4 |
0 |
0 |
T163 |
10167 |
7 |
0 |
0 |
T164 |
6680 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1692 |
0 |
0 |
T63 |
69700 |
110 |
0 |
0 |
T102 |
9412 |
22 |
0 |
0 |
T106 |
66700 |
142 |
0 |
0 |
T117 |
62573 |
90 |
0 |
0 |
T125 |
6914 |
17 |
0 |
0 |
T152 |
7318 |
16 |
0 |
0 |
T154 |
12726 |
34 |
0 |
0 |
T162 |
5735 |
7 |
0 |
0 |
T163 |
10167 |
25 |
0 |
0 |
T164 |
6680 |
5 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1425 |
0 |
0 |
T63 |
69700 |
109 |
0 |
0 |
T102 |
9412 |
15 |
0 |
0 |
T106 |
66700 |
62 |
0 |
0 |
T117 |
62573 |
42 |
0 |
0 |
T152 |
7318 |
36 |
0 |
0 |
T154 |
12726 |
43 |
0 |
0 |
T162 |
5735 |
17 |
0 |
0 |
T163 |
10167 |
26 |
0 |
0 |
T165 |
6533 |
30 |
0 |
0 |
T173 |
90472 |
240 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1324 |
0 |
0 |
T63 |
69700 |
58 |
0 |
0 |
T102 |
9412 |
10 |
0 |
0 |
T106 |
66700 |
60 |
0 |
0 |
T117 |
62573 |
24 |
0 |
0 |
T125 |
6914 |
3 |
0 |
0 |
T152 |
7318 |
28 |
0 |
0 |
T154 |
12726 |
9 |
0 |
0 |
T162 |
5735 |
7 |
0 |
0 |
T163 |
10167 |
14 |
0 |
0 |
T164 |
6680 |
4 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1400 |
0 |
0 |
T63 |
69700 |
58 |
0 |
0 |
T102 |
9412 |
18 |
0 |
0 |
T106 |
66700 |
48 |
0 |
0 |
T117 |
62573 |
21 |
0 |
0 |
T152 |
7318 |
25 |
0 |
0 |
T154 |
12726 |
44 |
0 |
0 |
T162 |
5735 |
1 |
0 |
0 |
T163 |
10167 |
31 |
0 |
0 |
T164 |
6680 |
2 |
0 |
0 |
T165 |
6533 |
3 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1435 |
0 |
0 |
T63 |
69700 |
69 |
0 |
0 |
T102 |
9412 |
10 |
0 |
0 |
T106 |
66700 |
103 |
0 |
0 |
T117 |
62573 |
50 |
0 |
0 |
T121 |
4069 |
7 |
0 |
0 |
T125 |
6914 |
14 |
0 |
0 |
T152 |
7318 |
16 |
0 |
0 |
T154 |
12726 |
41 |
0 |
0 |
T162 |
5735 |
2 |
0 |
0 |
T163 |
10167 |
20 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1916 |
0 |
0 |
T63 |
69700 |
169 |
0 |
0 |
T102 |
9412 |
42 |
0 |
0 |
T106 |
66700 |
246 |
0 |
0 |
T117 |
62573 |
106 |
0 |
0 |
T121 |
4069 |
6 |
0 |
0 |
T125 |
6914 |
18 |
0 |
0 |
T152 |
7318 |
13 |
0 |
0 |
T154 |
12726 |
31 |
0 |
0 |
T162 |
5735 |
17 |
0 |
0 |
T163 |
10167 |
48 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1365 |
0 |
0 |
T63 |
69700 |
64 |
0 |
0 |
T102 |
9412 |
28 |
0 |
0 |
T106 |
66700 |
48 |
0 |
0 |
T117 |
62573 |
14 |
0 |
0 |
T152 |
7318 |
43 |
0 |
0 |
T154 |
12726 |
42 |
0 |
0 |
T162 |
5735 |
2 |
0 |
0 |
T163 |
10167 |
18 |
0 |
0 |
T165 |
6533 |
22 |
0 |
0 |
T173 |
90472 |
242 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
2166 |
0 |
0 |
T63 |
69700 |
292 |
0 |
0 |
T102 |
9412 |
36 |
0 |
0 |
T106 |
66700 |
329 |
0 |
0 |
T117 |
62573 |
117 |
0 |
0 |
T121 |
4069 |
19 |
0 |
0 |
T152 |
7318 |
1 |
0 |
0 |
T154 |
12726 |
6 |
0 |
0 |
T162 |
5735 |
2 |
0 |
0 |
T163 |
10167 |
67 |
0 |
0 |
T164 |
6680 |
6 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1563 |
0 |
0 |
T63 |
69700 |
102 |
0 |
0 |
T102 |
9412 |
10 |
0 |
0 |
T106 |
66700 |
115 |
0 |
0 |
T117 |
62573 |
67 |
0 |
0 |
T121 |
4069 |
1 |
0 |
0 |
T125 |
6914 |
11 |
0 |
0 |
T152 |
7318 |
7 |
0 |
0 |
T154 |
12726 |
35 |
0 |
0 |
T162 |
5735 |
3 |
0 |
0 |
T163 |
10167 |
23 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1384 |
0 |
0 |
T63 |
69700 |
58 |
0 |
0 |
T102 |
9412 |
13 |
0 |
0 |
T106 |
66700 |
90 |
0 |
0 |
T113 |
16343 |
3 |
0 |
0 |
T117 |
62573 |
44 |
0 |
0 |
T121 |
4069 |
7 |
0 |
0 |
T152 |
7318 |
39 |
0 |
0 |
T154 |
12726 |
47 |
0 |
0 |
T162 |
5735 |
7 |
0 |
0 |
T163 |
10167 |
16 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1429 |
0 |
0 |
T63 |
69700 |
93 |
0 |
0 |
T102 |
9412 |
14 |
0 |
0 |
T106 |
66700 |
75 |
0 |
0 |
T116 |
20087 |
9 |
0 |
0 |
T117 |
62573 |
32 |
0 |
0 |
T152 |
7318 |
16 |
0 |
0 |
T154 |
12726 |
51 |
0 |
0 |
T162 |
5735 |
11 |
0 |
0 |
T163 |
10167 |
17 |
0 |
0 |
T164 |
6680 |
7 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1387 |
0 |
0 |
T63 |
69700 |
84 |
0 |
0 |
T102 |
9412 |
18 |
0 |
0 |
T106 |
66700 |
72 |
0 |
0 |
T117 |
62573 |
51 |
0 |
0 |
T125 |
6914 |
4 |
0 |
0 |
T152 |
7318 |
30 |
0 |
0 |
T154 |
12726 |
42 |
0 |
0 |
T162 |
5735 |
2 |
0 |
0 |
T163 |
10167 |
7 |
0 |
0 |
T164 |
6680 |
8 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1535 |
0 |
0 |
T63 |
69700 |
80 |
0 |
0 |
T102 |
9412 |
14 |
0 |
0 |
T106 |
66700 |
86 |
0 |
0 |
T117 |
62573 |
36 |
0 |
0 |
T121 |
4069 |
1 |
0 |
0 |
T125 |
6914 |
6 |
0 |
0 |
T152 |
7318 |
11 |
0 |
0 |
T154 |
12726 |
61 |
0 |
0 |
T162 |
5735 |
10 |
0 |
0 |
T163 |
10167 |
23 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1323 |
0 |
0 |
T63 |
69700 |
53 |
0 |
0 |
T102 |
9412 |
19 |
0 |
0 |
T106 |
66700 |
91 |
0 |
0 |
T117 |
62573 |
26 |
0 |
0 |
T125 |
6914 |
12 |
0 |
0 |
T152 |
7318 |
35 |
0 |
0 |
T154 |
12726 |
23 |
0 |
0 |
T162 |
5735 |
9 |
0 |
0 |
T163 |
10167 |
13 |
0 |
0 |
T164 |
6680 |
8 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462637985 |
1600 |
0 |
0 |
T63 |
69700 |
74 |
0 |
0 |
T102 |
9412 |
12 |
0 |
0 |
T106 |
66700 |
64 |
0 |
0 |
T117 |
62573 |
74 |
0 |
0 |
T121 |
4069 |
5 |
0 |
0 |
T125 |
6914 |
4 |
0 |
0 |
T152 |
7318 |
47 |
0 |
0 |
T154 |
12726 |
55 |
0 |
0 |
T162 |
5735 |
11 |
0 |
0 |
T163 |
10167 |
14 |
0 |
0 |