Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3634781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4371476

1

T1

893

T2

2

T3

1633

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4468779	1			T1	30		T2	1		T3	1470
values[0x0]	1766870	1			T1	468		T2	4		T3	445
values[0x1]	1770608	1			T1	416		T3	446		T4	11147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2592177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5414080

1

T1

896

T2

3

T3

1803

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30443	1			T3	7		T4	95		T5	5
valid_sources[0x01]	30609	1			T3	11		T4	392		T5	1
valid_sources[0x02]	28285	1			T3	20		T4	172		T5	6
valid_sources[0x03]	29756	1			T3	9		T4	322		T5	4
valid_sources[0x04]	28910	1			T3	7		T4	19		T5	1
valid_sources[0x05]	29597	1			T3	7		T4	242		T5	1
valid_sources[0x06]	28531	1			T3	10		T4	173		T5	4
valid_sources[0x07]	29323	1			T3	6		T4	32		T5	1
valid_sources[0x08]	30119	1			T3	8		T4	357		T5	4
valid_sources[0x09]	29055	1			T3	12		T4	179		T5	5
valid_sources[0x0a]	31734	1			T3	6		T4	145		T7	8
valid_sources[0x0b]	31464	1			T3	6		T4	5		T5	2
valid_sources[0x0c]	34979	1			T3	6		T4	226		T5	6
valid_sources[0x0d]	30914	1			T3	6		T4	309		T5	1
valid_sources[0x0e]	34512	1			T3	4		T4	766		T5	4
valid_sources[0x0f]	28777	1			T3	10		T4	212		T5	6
valid_sources[0x10]	29612	1			T3	14		T4	165		T5	3
valid_sources[0x11]	32895	1			T3	20		T4	16		T7	23
valid_sources[0x12]	31974	1			T3	17		T4	58		T5	3
valid_sources[0x13]	28468	1			T3	8		T4	148		T5	2
valid_sources[0x14]	29612	1			T3	3		T4	50		T5	4
valid_sources[0x15]	28437	1			T3	8		T4	98		T5	3
valid_sources[0x16]	31827	1			T3	14		T4	678		T5	4
valid_sources[0x17]	28531	1			T3	5		T4	113		T7	4
valid_sources[0x18]	28990	1			T3	14		T4	33		T5	5
valid_sources[0x19]	36159	1			T3	4		T4	330		T5	2
valid_sources[0x1a]	27022	1			T3	13		T4	130		T5	5
valid_sources[0x1b]	32420	1			T3	8		T4	111		T5	6
valid_sources[0x1c]	32494	1			T3	20		T4	546		T5	1
valid_sources[0x1d]	29369	1			T3	6		T4	87		T5	2
valid_sources[0x1e]	30923	1			T3	12		T4	180		T5	4
valid_sources[0x1f]	43914	1			T3	14		T4	211		T6	416
valid_sources[0x20]	106359	1			T3	5		T4	135		T5	3
valid_sources[0x21]	31115	1			T3	5		T4	152		T5	13
valid_sources[0x22]	31684	1			T3	13		T4	221		T5	4
valid_sources[0x23]	30043	1			T3	11		T4	178		T5	1
valid_sources[0x24]	29118	1			T3	7		T4	110		T5	1
valid_sources[0x25]	27711	1			T3	14		T4	104		T5	5
valid_sources[0x26]	31833	1			T3	16		T4	161		T5	3
valid_sources[0x27]	34541	1			T3	7		T4	301		T5	6
valid_sources[0x28]	29301	1			T3	8		T4	26		T5	1
valid_sources[0x29]	34708	1			T3	9		T4	94		T5	3
valid_sources[0x2a]	34129	1			T3	11		T4	232		T5	3
valid_sources[0x2b]	27055	1			T1	4		T3	6		T4	103
valid_sources[0x2c]	29505	1			T3	17		T4	926		T7	10
valid_sources[0x2d]	28919	1			T3	11		T4	9		T5	2
valid_sources[0x2e]	30038	1			T3	11		T4	91		T7	8
valid_sources[0x2f]	28583	1			T3	3		T4	102		T5	4
valid_sources[0x30]	30513	1			T3	10		T4	3		T5	6
valid_sources[0x31]	30495	1			T3	5		T4	273		T5	6
valid_sources[0x32]	41258	1			T3	5		T4	341		T5	5
valid_sources[0x33]	29514	1			T3	14		T4	66		T5	2
valid_sources[0x34]	29501	1			T3	12		T4	144		T7	10
valid_sources[0x35]	33229	1			T3	2		T4	81		T5	2
valid_sources[0x36]	29931	1			T3	9		T4	66		T5	2
valid_sources[0x37]	30766	1			T3	1		T4	162		T5	6
valid_sources[0x38]	31755	1			T3	8		T4	25		T5	7
valid_sources[0x39]	29876	1			T3	8		T4	114		T5	2
valid_sources[0x3a]	32341	1			T3	12		T4	84		T5	4
valid_sources[0x3b]	28855	1			T3	6		T4	111		T5	7
valid_sources[0x3c]	29813	1			T3	8		T4	309		T5	3
valid_sources[0x3d]	29933	1			T3	19		T4	104		T5	1
valid_sources[0x3e]	27646	1			T3	14		T4	31		T5	1
valid_sources[0x3f]	29195	1			T3	7		T4	179		T5	1
valid_sources[0x40]	28779	1			T3	13		T4	153		T5	2
valid_sources[0x41]	29946	1			T3	6		T4	202		T5	2
valid_sources[0x42]	28949	1			T3	7		T4	245		T5	4
valid_sources[0x43]	30695	1			T3	6		T4	375		T5	6
valid_sources[0x44]	29034	1			T3	9		T4	252		T5	7
valid_sources[0x45]	30835	1			T3	7		T4	214		T5	2
valid_sources[0x46]	28723	1			T3	17		T4	106		T5	5
valid_sources[0x47]	30201	1			T3	10		T4	59		T5	3
valid_sources[0x48]	45882	1			T3	10		T4	143		T5	3
valid_sources[0x49]	33718	1			T3	7		T4	380		T5	1
valid_sources[0x4a]	29067	1			T3	9		T4	116		T5	2
valid_sources[0x4b]	31277	1			T3	4		T4	36		T5	1
valid_sources[0x4c]	28800	1			T3	1		T4	143		T5	3
valid_sources[0x4d]	29045	1			T3	13		T4	242		T5	1
valid_sources[0x4e]	37485	1			T3	6		T4	106		T5	3
valid_sources[0x4f]	29481	1			T3	20		T4	12		T5	2
valid_sources[0x50]	29640	1			T3	10		T4	99		T5	3
valid_sources[0x51]	35083	1			T3	8		T5	1		T7	14
valid_sources[0x52]	28358	1			T3	6		T4	32		T5	5
valid_sources[0x53]	29157	1			T3	18		T4	157		T5	1
valid_sources[0x54]	30260	1			T3	9		T4	163		T5	2
valid_sources[0x55]	31708	1			T3	9		T4	257		T5	10
valid_sources[0x56]	28210	1			T3	10		T4	103		T7	17
valid_sources[0x57]	29279	1			T3	10		T4	78		T5	3
valid_sources[0x58]	27719	1			T3	12		T4	109		T5	5
valid_sources[0x59]	30019	1			T3	1		T4	47		T5	7
valid_sources[0x5a]	31855	1			T3	8		T4	17		T5	9
valid_sources[0x5b]	30895	1			T3	4		T4	167		T5	2
valid_sources[0x5c]	27780	1			T3	12		T4	96		T5	2
valid_sources[0x5d]	53176	1			T3	5		T4	150		T5	8
valid_sources[0x5e]	28793	1			T3	17		T4	172		T5	3
valid_sources[0x5f]	29071	1			T3	4		T4	297		T5	2
valid_sources[0x60]	29477	1			T3	5		T4	206		T7	17
valid_sources[0x61]	28354	1			T3	3		T4	47		T7	4
valid_sources[0x62]	28183	1			T1	455		T3	13		T4	144
valid_sources[0x63]	32729	1			T3	11		T4	64		T5	5
valid_sources[0x64]	31640	1			T3	12		T4	275		T5	4
valid_sources[0x65]	30099	1			T3	16		T4	57		T5	6
valid_sources[0x66]	29110	1			T3	12		T4	210		T5	1
valid_sources[0x67]	27878	1			T3	11		T4	40		T5	4
valid_sources[0x68]	33302	1			T3	3		T4	223		T5	4
valid_sources[0x69]	33012	1			T3	8		T4	348		T5	2
valid_sources[0x6a]	31279	1			T3	13		T4	41		T5	1
valid_sources[0x6b]	30743	1			T3	9		T4	49		T5	2
valid_sources[0x6c]	33578	1			T3	6		T4	54		T5	4
valid_sources[0x6d]	35592	1			T3	3		T4	256		T5	1
valid_sources[0x6e]	36289	1			T1	455		T3	12		T4	242
valid_sources[0x6f]	27187	1			T3	11		T4	300		T5	5
valid_sources[0x70]	28464	1			T3	9		T4	40		T5	2
valid_sources[0x71]	28156	1			T3	14		T4	113		T5	6
valid_sources[0x72]	25930	1			T3	14		T4	199		T5	1
valid_sources[0x73]	28614	1			T3	6		T4	27		T5	4
valid_sources[0x74]	35206	1			T3	11		T4	395		T5	5
valid_sources[0x75]	27665	1			T3	11		T4	32		T5	2
valid_sources[0x76]	30062	1			T3	22		T4	70		T5	2
valid_sources[0x77]	31485	1			T3	12		T4	278		T5	1
valid_sources[0x78]	35445	1			T3	11		T4	205		T5	8
valid_sources[0x79]	29454	1			T3	8		T4	745		T5	1
valid_sources[0x7a]	29538	1			T3	9		T4	58		T5	8
valid_sources[0x7b]	32637	1			T3	5		T4	55		T5	5
valid_sources[0x7c]	29521	1			T3	7		T4	714		T5	5
valid_sources[0x7d]	30529	1			T3	7		T4	35		T5	4
valid_sources[0x7e]	29479	1			T3	9		T4	197		T5	1
valid_sources[0x7f]	28172	1			T3	17		T4	148		T5	4
valid_sources[0x80]	31553	1			T3	3		T4	206		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1165048

1

T1

12

T3

757

T4

2400

values[0x0]

all_enables

biggest_size

1614029

1

T1

467

T2

2

T3

440

values[0x1]

all_enables

biggest_size

1592399

1

T1

414

T3

436

T4

9730