Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3654621

1

T1

21

T2

3

T3

728

full_word

4372573

1

T1

893

T2

2

T3

1633

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8026834	1			T1	914		T2	5		T3	2361
auto[TlIntgErrCmd]	101	1			T98	3		T100	7		T101	4
auto[TlIntgErrData]	128	1			T98	9		T100	8		T101	13
auto[TlIntgErrBoth]	131	1			T98	8		T100	5		T101	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4471829

1

T1

30

T2

1

T3

1470

auto[1]

3555365

1

T1

884

T2

4

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3306397	1			T1	18		T2	1		T3	713
auto[TlIntgErrNone]	partial	auto[1]	347901	1			T1	3		T2	2		T3	15
auto[TlIntgErrNone]	full_word	auto[0]	1165265	1			T1	12		T3	757		T4	2400
auto[TlIntgErrNone]	full_word	auto[1]	3207271	1			T1	881		T2	2		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T98	2		T100	4		T101	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T98	1		T100	1		T101	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T100	1		T112	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T100	1		T176	1		T150	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T98	3		T100	4		T101	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T98	5		T100	3		T101	5
auto[TlIntgErrData]	full_word	auto[0]	10	1			T100	1		T101	3		T181	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T98	1		T101	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T98	4		T100	2		T101	4
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T98	4		T100	2		T101	8
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T101	1		T176	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T100	1		T182	2		-	-