Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	631012982	3401562	0	0
gen_wmask[1].MaskCheckPortA_A	631012982	3401562	0	0
gen_wmask[2].MaskCheckPortA_A	631012982	3401562	0	0
gen_wmask[3].MaskCheckPortA_A	631012982	3401562	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631012982	3401562	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	1103012	15862	0	0
T5	170835	832	0	0
T6	814948	2720	0	0
T7	175165	832	0	0
T8	229840	2617	0	0
T9	1760344	12967	0	0
T10	1339	0	0	0
T11	126681	4762	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0
T38	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631012982	3401562	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	1103012	15862	0	0
T5	170835	832	0	0
T6	814948	2720	0	0
T7	175165	832	0	0
T8	229840	2617	0	0
T9	1760344	12967	0	0
T10	1339	0	0	0
T11	126681	4762	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0
T38	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631012982	3401562	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	1103012	15862	0	0
T5	170835	832	0	0
T6	814948	2720	0	0
T7	175165	832	0	0
T8	229840	2617	0	0
T9	1760344	12967	0	0
T10	1339	0	0	0
T11	126681	4762	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0
T38	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631012982	3401562	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	1103012	15862	0	0
T5	170835	832	0	0
T6	814948	2720	0	0
T7	175165	832	0	0
T8	229840	2617	0	0
T9	1760344	12967	0	0
T10	1339	0	0	0
T11	126681	4762	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0
T38	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	479165596	2119173	0	0
gen_wmask[1].MaskCheckPortA_A	479165596	2119173	0	0
gen_wmask[2].MaskCheckPortA_A	479165596	2119173	0	0
gen_wmask[3].MaskCheckPortA_A	479165596	2119173	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2119173	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	10491	0	0
T5	87129	832	0	0
T6	700012	1664	0	0
T7	46653	832	0	0
T8	154984	742	0	0
T9	927264	9984	0	0
T10	1339	0	0	0
T11	0	1081	0	0
T38	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2119173	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	10491	0	0
T5	87129	832	0	0
T6	700012	1664	0	0
T7	46653	832	0	0
T8	154984	742	0	0
T9	927264	9984	0	0
T10	1339	0	0	0
T11	0	1081	0	0
T38	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2119173	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	10491	0	0
T5	87129	832	0	0
T6	700012	1664	0	0
T7	46653	832	0	0
T8	154984	742	0	0
T9	927264	9984	0	0
T10	1339	0	0	0
T11	0	1081	0	0
T38	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2119173	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	10491	0	0
T5	87129	832	0	0
T6	700012	1664	0	0
T7	46653	832	0	0
T8	154984	742	0	0
T9	927264	9984	0	0
T10	1339	0	0	0
T11	0	1081	0	0
T38	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	151847386	1282389	0	0
gen_wmask[1].MaskCheckPortA_A	151847386	1282389	0	0
gen_wmask[2].MaskCheckPortA_A	151847386	1282389	0	0
gen_wmask[3].MaskCheckPortA_A	151847386	1282389	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	1282389	0	0
T4	918792	5371	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	1875	0	0
T9	833080	2983	0	0
T11	126681	3681	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	1282389	0	0
T4	918792	5371	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	1875	0	0
T9	833080	2983	0	0
T11	126681	3681	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	1282389	0	0
T4	918792	5371	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	1875	0	0
T9	833080	2983	0	0
T11	126681	3681	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	1282389	0	0
T4	918792	5371	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	1875	0	0
T9	833080	2983	0	0
T11	126681	3681	0	0
T12	1224	22	0	0
T13	21733	0	0	0
T14	119630	9806	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	218	0	0