Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	2919471	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	2919471	0	0
T1	3754	1663	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	14151	0	0
T5	87129	1663	0	0
T6	700012	3326	0	0
T7	46653	1670	0	0
T8	154984	0	0	0
T9	927264	14163	0	0
T10	1339	0	0	0
T13	0	832	0	0
T14	0	14968	0	0
T38	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	3247459	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	3247459	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	23813	0	0
T5	87129	832	0	0
T6	700012	1664	0	0
T7	46653	840	0	0
T8	154984	0	0	0
T9	927264	30399	0	0
T10	1339	0	0	0
T13	0	832	0	0
T14	0	8320	0	0
T38	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	195484	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	195484	0	0
T4	184220	879	0	0
T5	87129	0	0	0
T6	700012	192	0	0
T7	46653	0	0	0
T8	154984	486	0	0
T9	927264	204	0	0
T10	1339	0	0	0
T11	429049	952	0	0
T12	2193	6	0	0
T14	0	1451	0	0
T15	0	97	0	0
T25	0	160	0	0
T31	0	57	0	0
T38	3111	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	439837	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	439837	0	0
T4	184220	4109	0	0
T5	87129	0	0	0
T6	700012	192	0	0
T7	46653	0	0	0
T8	154984	486	0	0
T9	927264	932	0	0
T10	1339	0	0	0
T11	429049	952	0	0
T12	2193	6	0	0
T14	0	1447	0	0
T15	0	445	0	0
T25	0	160	0	0
T31	0	57	0	0
T38	3111	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	6308634	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	6308634	0	0
T1	3754	82	0	0
T2	720	5	0	0
T3	39903	1529	0	0
T4	184220	40531	0	0
T5	87129	61	0	0
T6	700012	1123	0	0
T7	46653	1608	0	0
T8	154984	3708	0	0
T9	927264	2494	0	0
T10	1339	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481283554	13164385	0	0
DepthKnown_A	481283554	481155070	0	0
RvalidKnown_A	481283554	481155070	0	0
WreadyKnown_A	481283554	481155070	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	13164385	0	0
T1	3754	82	0	0
T2	720	14	0	0
T3	39903	1529	0	0
T4	184220	159195	0	0
T5	87129	181	0	0
T6	700012	1121	0	0
T7	46653	6964	0	0
T8	154984	3696	0	0
T9	927264	10886	0	0
T10	1339	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481283554	481155070	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0