Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T11
1	0	Unreachable
1	1	Covered	T4,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	782860368	629470254	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	782860368	3811866	0	0
GntImpliesValid_A	782860368	3811866	0	0
GrantKnown_A	782860368	629470254	0	0
IdxKnown_A	782860368	629470254	0	0
IndexIsCorrect_A	782860368	3811866	0	0
LockArbDecision_A	782860368	0	0	0
NoReadyValidNoGrant_A	782860368	0	0	0
ReadyAndValidImplyGrant_A	782860368	3811866	0	0
ReqAndReadyImplyGrant_A	782860368	3811866	0	0
ReqImpliesValid_A	782860368	3811866	0	0
ReqStaysHighUntilGranted0_M	782860368	0	0	0
RoundRobin_A	782860368	4	0	955
ValidKnown_A	782860368	629470254	0	0
gen_data_port_assertion.DataFlow_A	782860368	3811866	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	629470254	0	0
T1	3866	3808	0	0
T2	720	631	0	0
T3	50635	50542	0	0
T4	2021804	1096732	0	0
T5	254541	170765	0	0
T6	929884	814460	0	0
T7	303677	175076	0	0
T8	304696	226640	0	0
T9	2593424	1757199	0	0
T10	1339	1240	0	0
T11	253362	121096	0	0
T12	2448	1224	0	0
T13	21733	21696	0	0
T14	119630	1189606	0	0
T15	0	96634	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	629470254	0	0
T1	3866	3808	0	0
T2	720	631	0	0
T3	50635	50542	0	0
T4	2021804	1096732	0	0
T5	254541	170765	0	0
T6	929884	814460	0	0
T7	303677	175076	0	0
T8	304696	226640	0	0
T9	2593424	1757199	0	0
T10	1339	1240	0	0
T11	253362	121096	0	0
T12	2448	1224	0	0
T13	21733	21696	0	0
T14	119630	1189606	0	0
T15	0	96634	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	629470254	0	0
T1	3866	3808	0	0
T2	720	631	0	0
T3	50635	50542	0	0
T4	2021804	1096732	0	0
T5	254541	170765	0	0
T6	929884	814460	0	0
T7	303677	175076	0	0
T8	304696	226640	0	0
T9	2593424	1757199	0	0
T10	1339	1240	0	0
T11	253362	121096	0	0
T12	2448	1224	0	0
T13	21733	21696	0	0
T14	119630	1189606	0	0
T15	0	96634	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	4	0	955
T17	353819	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	7811	0	0	1
T58	2074	0	0	1
T59	486920	0	0	1
T60	440938	0	0	1
T61	953284	0	0	1
T62	70754	0	0	1
T63	617979	0	0	1
T64	125152	0	0	1
T65	6044	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	629470254	0	0
T1	3866	3808	0	0
T2	720	631	0	0
T3	50635	50542	0	0
T4	2021804	1096732	0	0
T5	254541	170765	0	0
T6	929884	814460	0	0
T7	303677	175076	0	0
T8	304696	226640	0	0
T9	2593424	1757199	0	0
T10	1339	1240	0	0
T11	253362	121096	0	0
T12	2448	1224	0	0
T13	21733	21696	0	0
T14	119630	1189606	0	0
T15	0	96634	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782860368	3811866	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	2021804	18219	0	0
T5	254541	832	0	0
T6	929884	2917	0	0
T7	303677	832	0	0
T8	304696	3906	0	0
T9	2593424	13195	0	0
T10	1339	0	0	0
T11	253362	6902	0	0
T12	2448	45	0	0
T13	43466	0	0	0
T14	239260	11281	0	0
T15	0	396	0	0
T25	0	649	0	0
T31	0	245	0	0
T32	0	136	0	0
T38	0	832	0	0
T46	0	522	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0
T53	0	776	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T11
1	0	Unreachable
1	1	Covered	T4,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T8,T11
0	0	1	Unreachable
0	0	0	Covered	T4,T8,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151847386	29806962	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	151847386	667539	0	0
GntImpliesValid_A	151847386	667539	0	0
GrantKnown_A	151847386	29806962	0	0
IdxKnown_A	151847386	29806962	0	0
IndexIsCorrect_A	151847386	667539	0	0
LockArbDecision_A	151847386	0	0	0
NoReadyValidNoGrant_A	151847386	0	0	0
ReadyAndValidImplyGrant_A	151847386	667539	0	0
ReqAndReadyImplyGrant_A	151847386	667539	0	0
ReqImpliesValid_A	151847386	667539	0	0
ReqStaysHighUntilGranted0_M	151847386	0	0	0
RoundRobin_A	151847386	0	0	0
ValidKnown_A	151847386	29806962	0	0
gen_data_port_assertion.DataFlow_A	151847386	667539	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	29806962	0	0
T4	918792	117960	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	71752	0	0
T9	833080	0	0	0
T11	126681	121096	0	0
T12	1224	1224	0	0
T13	21733	0	0	0
T14	119630	504480	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	29806962	0	0
T4	918792	117960	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	71752	0	0
T9	833080	0	0	0
T11	126681	121096	0	0
T12	1224	1224	0	0
T13	21733	0	0	0
T14	119630	504480	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	29806962	0	0
T4	918792	117960	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	71752	0	0
T9	833080	0	0	0
T11	126681	121096	0	0
T12	1224	1224	0	0
T13	21733	0	0	0
T14	119630	504480	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	29806962	0	0
T4	918792	117960	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	71752	0	0
T9	833080	0	0	0
T11	126681	121096	0	0
T12	1224	1224	0	0
T13	21733	0	0	0
T14	119630	504480	0	0
T27	0	216	0	0
T30	0	504	0	0
T31	0	3040	0	0
T32	0	3584	0	0
T33	0	23264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	667539	0	0
T4	918792	3644	0	0
T5	83706	0	0	0
T6	114936	0	0	0
T7	128512	0	0	0
T8	74856	2678	0	0
T9	833080	0	0	0
T11	126681	4869	0	0
T12	1224	45	0	0
T13	21733	0	0	0
T14	119630	5332	0	0
T31	0	245	0	0
T32	0	136	0	0
T50	0	1121	0	0
T51	0	137	0	0
T52	0	5775	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T4,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151847386	120584554	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	151847386	836496	0	0
GntImpliesValid_A	151847386	836496	0	0
GrantKnown_A	151847386	120584554	0	0
IdxKnown_A	151847386	120584554	0	0
IndexIsCorrect_A	151847386	836496	0	0
LockArbDecision_A	151847386	0	0	0
NoReadyValidNoGrant_A	151847386	0	0	0
ReadyAndValidImplyGrant_A	151847386	836496	0	0
ReqAndReadyImplyGrant_A	151847386	836496	0	0
ReqImpliesValid_A	151847386	836496	0	0
ReqStaysHighUntilGranted0_M	151847386	0	0	0
RoundRobin_A	151847386	0	0	0
ValidKnown_A	151847386	120584554	0	0
gen_data_port_assertion.DataFlow_A	151847386	836496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	120584554	0	0
T1	112	112	0	0
T3	10732	10732	0	0
T4	918792	794560	0	0
T5	83706	83690	0	0
T6	114936	114511	0	0
T7	128512	128512	0	0
T8	74856	0	0	0
T9	833080	830013	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	0	21696	0	0
T14	0	685126	0	0
T15	0	96634	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	120584554	0	0
T1	112	112	0	0
T3	10732	10732	0	0
T4	918792	794560	0	0
T5	83706	83690	0	0
T6	114936	114511	0	0
T7	128512	128512	0	0
T8	74856	0	0	0
T9	833080	830013	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	0	21696	0	0
T14	0	685126	0	0
T15	0	96634	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	120584554	0	0
T1	112	112	0	0
T3	10732	10732	0	0
T4	918792	794560	0	0
T5	83706	83690	0	0
T6	114936	114511	0	0
T7	128512	128512	0	0
T8	74856	0	0	0
T9	833080	830013	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	0	21696	0	0
T14	0	685126	0	0
T15	0	96634	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	120584554	0	0
T1	112	112	0	0
T3	10732	10732	0	0
T4	918792	794560	0	0
T5	83706	83690	0	0
T6	114936	114511	0	0
T7	128512	128512	0	0
T8	74856	0	0	0
T9	833080	830013	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	0	21696	0	0
T14	0	685126	0	0
T15	0	96634	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151847386	836496	0	0
T4	918792	3188	0	0
T5	83706	0	0	0
T6	114936	1056	0	0
T7	128512	0	0	0
T8	74856	0	0	0
T9	833080	2983	0	0
T11	126681	0	0	0
T12	1224	0	0	0
T13	21733	0	0	0
T14	119630	5949	0	0
T15	0	396	0	0
T25	0	649	0	0
T39	0	7476	0	0
T45	0	5102	0	0
T46	0	522	0	0
T53	0	776	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	479165596	479078738	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	479165596	2307831	0	0
GntImpliesValid_A	479165596	2307831	0	0
GrantKnown_A	479165596	479078738	0	0
IdxKnown_A	479165596	479078738	0	0
IndexIsCorrect_A	479165596	2307831	0	0
LockArbDecision_A	479165596	0	0	0
NoReadyValidNoGrant_A	479165596	0	0	0
ReadyAndValidImplyGrant_A	479165596	2307831	0	0
ReqAndReadyImplyGrant_A	479165596	2307831	0	0
ReqImpliesValid_A	479165596	2307831	0	0
ReqStaysHighUntilGranted0_M	479165596	0	0	0
RoundRobin_A	479165596	4	0	955
ValidKnown_A	479165596	479078738	0	0
gen_data_port_assertion.DataFlow_A	479165596	2307831	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	479078738	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	479078738	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	479078738	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	4	0	955
T17	353819	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	7811	0	0	1
T58	2074	0	0	1
T59	486920	0	0	1
T60	440938	0	0	1
T61	953284	0	0	1
T62	70754	0	0	1
T63	617979	0	0	1
T64	125152	0	0	1
T65	6044	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	479078738	0	0
T1	3754	3696	0	0
T2	720	631	0	0
T3	39903	39810	0	0
T4	184220	184212	0	0
T5	87129	87075	0	0
T6	700012	699949	0	0
T7	46653	46564	0	0
T8	154984	154888	0	0
T9	927264	927186	0	0
T10	1339	1240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479165596	2307831	0	0
T1	3754	832	0	0
T2	720	0	0	0
T3	39903	832	0	0
T4	184220	11387	0	0
T5	87129	832	0	0
T6	700012	1861	0	0
T7	46653	832	0	0
T8	154984	1228	0	0
T9	927264	10212	0	0
T10	1339	0	0	0
T11	0	2033	0	0
T38	0	832	0	0