Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3849536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4400021

1

T1

1484

T2

3433

T3

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4589025	1			T1	4128		T2	5132		T3	177
values[0x0]	1828218	1			T1	763		T2	428		T3	37
values[0x1]	1832314	1			T1	727		T2	462		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2726357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5523200

1

T1

2777

T2

3961

T3

89

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29711	1			T1	19		T2	21		T5	5
valid_sources[0x01]	39007	1			T1	20		T2	16		T5	3
valid_sources[0x02]	30876	1			T1	15		T2	23		T5	7
valid_sources[0x03]	33472	1			T1	24		T2	32		T3	2
valid_sources[0x04]	31994	1			T1	19		T2	13		T3	1
valid_sources[0x05]	31479	1			T1	23		T2	23		T3	1
valid_sources[0x06]	30731	1			T1	25		T2	23		T3	1
valid_sources[0x07]	28751	1			T1	25		T2	24		T5	3
valid_sources[0x08]	29933	1			T1	19		T2	29		T5	7
valid_sources[0x09]	27946	1			T1	17		T2	23		T3	3
valid_sources[0x0a]	28773	1			T1	19		T2	26		T3	4
valid_sources[0x0b]	36999	1			T1	23		T2	21		T5	3
valid_sources[0x0c]	32025	1			T1	15		T2	20		T3	1
valid_sources[0x0d]	29354	1			T1	22		T2	33		T3	2
valid_sources[0x0e]	31375	1			T1	30		T2	17		T5	3
valid_sources[0x0f]	29252	1			T1	28		T2	17		T5	2
valid_sources[0x10]	33746	1			T1	22		T2	20		T3	2
valid_sources[0x11]	29585	1			T1	20		T2	18		T3	2
valid_sources[0x12]	30639	1			T1	19		T2	21		T3	2
valid_sources[0x13]	30542	1			T1	29		T2	27		T5	4
valid_sources[0x14]	29887	1			T1	21		T2	25		T3	3
valid_sources[0x15]	32063	1			T1	27		T2	20		T5	3
valid_sources[0x16]	45778	1			T1	16		T2	18		T5	6
valid_sources[0x17]	31310	1			T1	13		T2	17		T5	3
valid_sources[0x18]	34635	1			T1	30		T2	26		T5	1
valid_sources[0x19]	29477	1			T1	17		T2	23		T3	1
valid_sources[0x1a]	35493	1			T1	15		T2	19		T5	4
valid_sources[0x1b]	33680	1			T1	24		T2	26		T3	3
valid_sources[0x1c]	33924	1			T1	17		T2	30		T5	3
valid_sources[0x1d]	33492	1			T1	12		T2	14		T5	4
valid_sources[0x1e]	30655	1			T1	25		T2	20		T5	3
valid_sources[0x1f]	31879	1			T1	27		T2	21		T5	4
valid_sources[0x20]	30053	1			T1	23		T2	24		T3	1
valid_sources[0x21]	28840	1			T1	19		T2	23		T3	1
valid_sources[0x22]	30607	1			T1	25		T2	31		T5	4
valid_sources[0x23]	29351	1			T1	18		T2	32		T5	5
valid_sources[0x24]	36678	1			T1	14		T2	16		T5	8
valid_sources[0x25]	30460	1			T1	24		T2	18		T5	6
valid_sources[0x26]	31741	1			T1	17		T2	24		T5	3
valid_sources[0x27]	31073	1			T1	24		T2	31		T3	1
valid_sources[0x28]	34163	1			T1	25		T2	26		T5	5
valid_sources[0x29]	34901	1			T1	21		T2	28		T3	1
valid_sources[0x2a]	31318	1			T1	24		T2	24		T5	2
valid_sources[0x2b]	32663	1			T1	16		T2	24		T5	2
valid_sources[0x2c]	29876	1			T1	16		T2	28		T3	2
valid_sources[0x2d]	30189	1			T1	26		T2	21		T5	2
valid_sources[0x2e]	31214	1			T1	24		T2	27		T3	4
valid_sources[0x2f]	27639	1			T1	16		T2	13		T3	1
valid_sources[0x30]	28246	1			T1	25		T2	16		T5	4
valid_sources[0x31]	30198	1			T1	22		T2	30		T5	8
valid_sources[0x32]	32161	1			T1	24		T2	12		T5	2
valid_sources[0x33]	33133	1			T1	18		T2	23		T5	2
valid_sources[0x34]	34125	1			T1	24		T2	25		T5	2
valid_sources[0x35]	28725	1			T1	26		T2	30		T3	2
valid_sources[0x36]	30327	1			T1	25		T2	20		T3	1
valid_sources[0x37]	33326	1			T1	23		T2	17		T3	3
valid_sources[0x38]	30793	1			T1	23		T2	26		T5	2
valid_sources[0x39]	30130	1			T1	26		T2	23		T3	1
valid_sources[0x3a]	31252	1			T1	19		T2	26		T3	1
valid_sources[0x3b]	31446	1			T1	25		T2	29		T3	1
valid_sources[0x3c]	38156	1			T1	25		T2	26		T3	1
valid_sources[0x3d]	30113	1			T1	26		T2	30		T3	1
valid_sources[0x3e]	31559	1			T1	30		T2	23		T3	2
valid_sources[0x3f]	36353	1			T1	29		T2	19		T3	1
valid_sources[0x40]	31301	1			T1	20		T2	17		T5	6
valid_sources[0x41]	34317	1			T1	18		T2	17		T3	5
valid_sources[0x42]	30300	1			T1	29		T2	34		T3	1
valid_sources[0x43]	31840	1			T1	20		T2	26		T3	1
valid_sources[0x44]	28826	1			T1	19		T2	27		T5	1
valid_sources[0x45]	28077	1			T1	20		T2	26		T5	2
valid_sources[0x46]	32991	1			T1	16		T2	25		T5	7
valid_sources[0x47]	32132	1			T1	18		T2	22		T5	1
valid_sources[0x48]	27991	1			T1	8		T2	18		T3	5
valid_sources[0x49]	32144	1			T1	15		T2	28		T4	3
valid_sources[0x4a]	35058	1			T1	34		T2	25		T3	5
valid_sources[0x4b]	31374	1			T1	17		T2	22		T3	3
valid_sources[0x4c]	33106	1			T1	27		T2	28		T3	2
valid_sources[0x4d]	32150	1			T1	21		T2	27		T5	4
valid_sources[0x4e]	34304	1			T1	23		T2	26		T5	4
valid_sources[0x4f]	29265	1			T1	18		T2	26		T3	3
valid_sources[0x50]	32670	1			T1	19		T2	18		T5	4
valid_sources[0x51]	30640	1			T1	22		T2	30		T5	5
valid_sources[0x52]	32840	1			T1	18		T2	24		T3	3
valid_sources[0x53]	39047	1			T1	26		T2	20		T3	1
valid_sources[0x54]	32279	1			T1	10		T2	16		T3	1
valid_sources[0x55]	29987	1			T1	24		T2	32		T3	1
valid_sources[0x56]	52041	1			T1	17		T2	28		T3	1
valid_sources[0x57]	29763	1			T1	20		T2	14		T3	1
valid_sources[0x58]	32374	1			T1	28		T2	18		T5	1
valid_sources[0x59]	31002	1			T1	16		T2	23		T3	1
valid_sources[0x5a]	31587	1			T1	31		T2	14		T5	1
valid_sources[0x5b]	29984	1			T1	21		T2	14		T3	1
valid_sources[0x5c]	29747	1			T1	32		T2	24		T3	1
valid_sources[0x5d]	53833	1			T1	19		T2	28		T5	3
valid_sources[0x5e]	29762	1			T1	24		T2	28		T3	2
valid_sources[0x5f]	35796	1			T1	22		T2	25		T5	3
valid_sources[0x60]	31259	1			T1	22		T2	19		T5	2
valid_sources[0x61]	28938	1			T1	30		T2	13		T5	6
valid_sources[0x62]	30879	1			T1	25		T2	30		T3	2
valid_sources[0x63]	33549	1			T1	18		T2	19		T5	3
valid_sources[0x64]	32093	1			T1	24		T2	35		T5	3
valid_sources[0x65]	30209	1			T1	15		T2	19		T5	1
valid_sources[0x66]	33247	1			T1	28		T2	20		T3	6
valid_sources[0x67]	40912	1			T1	22		T2	35		T5	2
valid_sources[0x68]	43505	1			T1	23		T2	26		T3	1
valid_sources[0x69]	38874	1			T1	25		T2	21		T3	1
valid_sources[0x6a]	36504	1			T1	18		T2	28		T3	2
valid_sources[0x6b]	32919	1			T1	26		T2	35		T3	2
valid_sources[0x6c]	28145	1			T1	19		T2	27		T5	4
valid_sources[0x6d]	31851	1			T1	20		T2	29		T3	2
valid_sources[0x6e]	31334	1			T1	23		T2	25		T3	2
valid_sources[0x6f]	31260	1			T1	22		T2	29		T3	1
valid_sources[0x70]	33910	1			T1	19		T2	23		T5	3
valid_sources[0x71]	31809	1			T1	24		T2	16		T3	1
valid_sources[0x72]	33057	1			T1	17		T2	20		T3	2
valid_sources[0x73]	31925	1			T1	25		T2	24		T3	8
valid_sources[0x74]	36385	1			T1	25		T2	29		T3	1
valid_sources[0x75]	30963	1			T1	22		T2	24		T5	1
valid_sources[0x76]	30972	1			T1	33		T2	13		T5	6
valid_sources[0x77]	36014	1			T1	21		T2	19		T5	2
valid_sources[0x78]	37027	1			T1	13		T2	15		T5	1
valid_sources[0x79]	31344	1			T1	17		T2	18		T3	1
valid_sources[0x7a]	34912	1			T1	20		T2	25		T5	4
valid_sources[0x7b]	29701	1			T1	14		T2	28		T3	1
valid_sources[0x7c]	39907	1			T1	16		T2	17		T5	5
valid_sources[0x7d]	32179	1			T1	22		T2	26		T5	2
valid_sources[0x7e]	34551	1			T1	27		T2	27		T5	3
valid_sources[0x7f]	29694	1			T1	23		T2	16		T3	1
valid_sources[0x80]	31843	1			T1	28		T2	29		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1092725

1

T1

410

T2

2554

T3

30

values[0x0]

all_enables

biggest_size

1664070

1

T1

556

T2

422

T3

7

values[0x1]

all_enables

biggest_size

1643226

1

T1

518

T2

457

T3

3