Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3868461

1

T1

4134

T2

2589

T3

195

full_word

4401129

1

T1

1484

T2

3433

T3

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8269180	1			T1	5618		T2	6022		T3	235
auto[TlIntgErrCmd]	135	1			T64	10		T94	10		T95	8
auto[TlIntgErrData]	129	1			T64	11		T94	7		T95	6
auto[TlIntgErrBoth]	146	1			T64	9		T94	13		T95	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4592397

1

T1

4128

T2

5132

T3

177

auto[1]

3677193

1

T1

1490

T2

890

T3

58

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3499218	1			T1	3718		T2	2578		T3	147
auto[TlIntgErrNone]	partial	auto[1]	368873	1			T1	416		T2	11		T3	48
auto[TlIntgErrNone]	full_word	auto[0]	1093002	1			T1	410		T2	2554		T3	30
auto[TlIntgErrNone]	full_word	auto[1]	3308087	1			T1	1074		T2	879		T3	10
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T64	3		T94	4		T95	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T64	5		T94	5		T95	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T171	1		T172	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T64	2		T94	1		T169	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T64	3		T94	3		T95	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T64	4		T94	3		T95	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T64	3		T94	1		T151	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T64	1		T169	1		T170	3
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T64	4		T94	2		T151	5
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T64	5		T94	10		T95	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T94	1		T173	1		T174	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T95	1		T170	1		T175	1