Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	635327142	3500456	0	0
gen_wmask[1].MaskCheckPortA_A	635327142	3500456	0	0
gen_wmask[2].MaskCheckPortA_A	635327142	3500456	0	0
gen_wmask[3].MaskCheckPortA_A	635327142	3500456	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635327142	3500456	0	0
T1	380898	1787	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	102	0	0
T8	8954	136	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4747	0	0
T16	0	832	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T37	0	832	0	0
T39	0	10	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635327142	3500456	0	0
T1	380898	1787	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	102	0	0
T8	8954	136	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4747	0	0
T16	0	832	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T37	0	832	0	0
T39	0	10	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635327142	3500456	0	0
T1	380898	1787	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	102	0	0
T8	8954	136	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4747	0	0
T16	0	832	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T37	0	832	0	0
T39	0	10	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635327142	3500456	0	0
T1	380898	1787	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	102	0	0
T8	8954	136	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4747	0	0
T16	0	832	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T37	0	832	0	0
T39	0	10	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	486094311	2110448	0	0
gen_wmask[1].MaskCheckPortA_A	486094311	2110448	0	0
gen_wmask[2].MaskCheckPortA_A	486094311	2110448	0	0
gen_wmask[3].MaskCheckPortA_A	486094311	2110448	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2110448	0	0
T1	339680	510	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	9	0	0
T8	6694	18	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	1527	0	0
T16	0	832	0	0
T37	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2110448	0	0
T1	339680	510	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	9	0	0
T8	6694	18	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	1527	0	0
T16	0	832	0	0
T37	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2110448	0	0
T1	339680	510	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	9	0	0
T8	6694	18	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	1527	0	0
T16	0	832	0	0
T37	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2110448	0	0
T1	339680	510	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	9	0	0
T8	6694	18	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	1527	0	0
T16	0	832	0	0
T37	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	149232831	1390008	0	0
gen_wmask[1].MaskCheckPortA_A	149232831	1390008	0	0
gen_wmask[2].MaskCheckPortA_A	149232831	1390008	0	0
gen_wmask[3].MaskCheckPortA_A	149232831	1390008	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	1390008	0	0
T1	41218	1277	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	93	0	0
T8	2260	118	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	3220	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T39	0	10	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	1390008	0	0
T1	41218	1277	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	93	0	0
T8	2260	118	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	3220	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T39	0	10	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	1390008	0	0
T1	41218	1277	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	93	0	0
T8	2260	118	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	3220	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T39	0	10	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	1390008	0	0
T1	41218	1277	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	93	0	0
T8	2260	118	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	3220	0	0
T17	0	7797	0	0
T18	0	10395	0	0
T21	0	2736	0	0
T24	0	1909	0	0
T25	0	75	0	0
T39	0	10	0	0