Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	99.31	100.00	100.00			97.22	100.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.61	100.00	88.46			98.63	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_sck2csb_status	100.00	100.00				100.00
u_stage_to_commit	100.00	100.00				100.00
u_sw_status_update_sync	99.00	100.00	96.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	166	6	6	100.00
ALWAYS	177	8	8	100.00
ALWAYS	190	4	4	100.00
ALWAYS	202	7	7	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	264	3	3	100.00
ALWAYS	309	4	4	100.00
ALWAYS	322	5	5	100.00
ALWAYS	336	3	3	100.00
ALWAYS	344	6	6	100.00
CONT_ASSIGN	358	1	1	100.00
ALWAYS	365	3	3	100.00
ALWAYS	370	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
95	1	1
98	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
			MISSING_ELSE
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
			MISSING_ELSE
190	1	1
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
			MISSING_ELSE
208	1	1
209	1	1
			MISSING_ELSE
224	1	1
225	1	1
226	1	1
241	1	1
264	1	1
265	1	1
267	1	1
309	1	1
310	1	1
311	1	1
312	1	1
			MISSING_ELSE
322	1	1
323	1	1
324	1	1
326	1	1
327	1	1
336	1	1
337	1	1
339	1	1
344	1	1
346	1	1
348	1	1
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
			MISSING_ELSE
358	1	1
365	2	2
366	1	1
370	1	1
372	1	1
374	1	1
376	1	1
378	1	1
379	1	1
381	1	1
382	1	1
			MISSING_ELSE
387	1	1

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T10,T16
1	1	Covered	T2,T10,T17

 LINE       170
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T10,T16
1	Covered	T1,T2,T5

 LINE       183
 EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
             ----1----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T10,T16
1	1	Covered	T2,T10,T16

 LINE       183
 SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T10,T16
1	Covered	T1,T2,T5

 LINE       351
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T17,T18,T21
1	Covered	T17,T18,T21

 LINE       358
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Covered	T17,T18,T21
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T21

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		36	35	97.22
TERNARY	358	2	2	100.00
IF	166	4	4	100.00
IF	177	5	5	100.00
IF	190	3	3	100.00
IF	203	3	3	100.00
IF	208	2	2	100.00
IF	264	2	2	100.00
IF	309	3	3	100.00
IF	322	2	2	100.00
IF	336	2	2	100.00
IF	346	2	2	100.00
IF	365	2	2	100.00
CASE	376	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	358	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T17,T18,T21

	LineNo.	Expression
-1-:	166	if ((!sys_rst_ni))
-2-:	168	if (inclk_busy_set_i)
-3-:	170	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T21
0	0	1	Covered	T2,T10,T17
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	177	if ((!sys_rst_ni))
-2-:	179	if (inclk_we_set_i)
-3-:	181	if (inclk_we_clr_i)
-4-:	183	if ((sck_sw_we && (sck_sw_status[BitWe] == 1'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T17,T18,T21
0	0	1	-	Covered	T17,T18,T21
0	0	0	1	Covered	T2,T10,T16
0	0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	190	if ((!sys_rst_ni))
-2-:	192	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T10,T16
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	203	if (inclk_we_set_i)
-2-:	205	if (inclk_we_clr_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T18,T21
0	1	Covered	T17,T18,T21
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	208	if (inclk_busy_set_i)

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	264	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!sys_rst_ni))
-2-:	311	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	336	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	346	if (byte_sel_update)

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	376	case (st_q)
-2-:	378	if ((sel_dp_i == DpReadStatus))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Covered	T17,T18,T21
StIdle	0	Covered	T1,T2,T3
StActive	-	Covered	T17,T18,T21
default	-	Not Covered

---

Assert Coverage for Module : spid_status

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusyBitZero_A	956	956	0	0

BusyBitZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0