Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T2,T10,T17
1	0	Covered	T2,T10,T17
1	1	Covered	T2,T10,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T17
1	0	Covered	T2,T10,T17
1	1	Covered	T2,T10,T17

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1458282933	2966	0	0
SrcPulseCheck_M	447698493	2966	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1458282933	2966	0	0
T2	315338	7	0	0
T3	10756	0	0	0
T4	2330	0	0	0
T5	249050	0	0	0
T6	2164	0	0	0
T7	7672	0	0	0
T8	13388	0	0	0
T9	269452	0	0	0
T10	396502	5	0	0
T11	3488	0	0	0
T17	501231	13	0	0
T18	729721	21	0	0
T19	38536	0	0	0
T20	520318	0	0	0
T21	632841	10	0	0
T23	0	14	0	0
T24	477335	0	0	0
T25	20721	0	0	0
T28	0	20	0	0
T35	0	4	0	0
T36	0	7	0	0
T38	643830	0	0	0
T39	707396	6	0	0
T41	0	14	0	0
T45	0	1	0	0
T46	0	2	0	0
T61	1161	0	0	0
T134	0	7	0	0
T144	0	15	0	0
T145	0	7	0	0
T146	0	2	0	0
T147	0	7	0	0
T148	0	7	0	0
T149	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	447698493	2966	0	0
T2	51308	7	0	0
T5	485248	0	0	0
T7	3808	0	0	0
T8	4520	0	0	0
T9	131584	0	0	0
T10	63640	5	0	0
T11	144	0	0	0
T12	223452	0	0	0
T14	818978	0	0	0
T16	11828	0	0	0
T17	711808	13	0	0
T18	102788	21	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	10	0	0
T23	0	14	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	20	0	0
T35	0	4	0	0
T36	0	7	0	0
T38	106434	0	0	0
T39	115517	6	0	0
T40	45986	0	0	0
T41	0	14	0	0
T45	0	1	0	0
T46	0	2	0	0
T134	0	7	0	0
T144	0	15	0	0
T145	0	7	0	0
T146	0	2	0	0
T147	0	7	0	0
T148	0	7	0	0
T149	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T2,T10,T36
1	0	Covered	T2,T10,T36
1	1	Covered	T2,T10,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T36
1	0	Covered	T2,T10,T36
1	1	Covered	T2,T10,T36

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486094311	171	0	0
SrcPulseCheck_M	149232831	171	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	171	0	0
T2	157669	2	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	0	0	0
T6	1082	0	0	0
T7	3836	0	0	0
T8	6694	0	0	0
T9	134726	0	0	0
T10	198251	3	0	0
T11	1744	0	0	0
T36	0	2	0	0
T134	0	2	0	0
T144	0	8	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	171	0	0
T2	25654	2	0	0
T5	242624	0	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	0	0	0
T10	31820	3	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	0	0	0
T36	0	2	0	0
T134	0	2	0	0
T144	0	8	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T2,T10,T36
1	0	Covered	T2,T10,T36
1	1	Covered	T2,T10,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T36
1	0	Covered	T2,T10,T36
1	1	Covered	T2,T10,T36

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486094311	323	0	0
SrcPulseCheck_M	149232831	323	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	323	0	0
T2	157669	5	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	0	0	0
T6	1082	0	0	0
T7	3836	0	0	0
T8	6694	0	0	0
T9	134726	0	0	0
T10	198251	2	0	0
T11	1744	0	0	0
T36	0	5	0	0
T134	0	5	0	0
T144	0	7	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	323	0	0
T2	25654	5	0	0
T5	242624	0	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	0	0	0
T10	31820	2	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	0	0	0
T36	0	5	0	0
T134	0	5	0	0
T144	0	7	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T17,T18,T21
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T18,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T21
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T18,T21

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486094311	2472	0	0
SrcPulseCheck_M	149232831	2472	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2472	0	0
T17	501231	13	0	0
T18	729721	21	0	0
T19	38536	0	0	0
T20	520318	0	0	0
T21	632841	10	0	0
T23	0	14	0	0
T24	477335	0	0	0
T25	20721	0	0	0
T28	0	20	0	0
T35	0	4	0	0
T38	643830	0	0	0
T39	707396	6	0	0
T41	0	14	0	0
T45	0	1	0	0
T46	0	2	0	0
T61	1161	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	2472	0	0
T17	711808	13	0	0
T18	102788	21	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	10	0	0
T23	0	14	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	20	0	0
T35	0	4	0	0
T38	106434	0	0	0
T39	115517	6	0	0
T40	45986	0	0	0
T41	0	14	0	0
T45	0	1	0	0
T46	0	2	0	0