Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	2922603	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	2922603	0	0
T2	157669	1663	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	1663	0	0
T6	1082	0	0	0
T7	3836	0	0	0
T8	6694	0	0	0
T9	134726	1663	0	0
T10	198251	1854	0	0
T11	1744	0	0	0
T16	0	1663	0	0
T17	0	11643	0	0
T18	0	14154	0	0
T19	0	832	0	0
T20	0	832	0	0
T37	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	3236756	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	3236756	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	0	0	0
T8	6694	0	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T11	1744	0	0	0
T16	0	832	0	0
T17	0	7488	0	0
T18	0	36938	0	0
T19	0	3659	0	0
T20	0	832	0	0
T37	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	197414	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	197414	0	0
T1	339680	330	0	0
T2	157669	0	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	0	0	0
T6	1082	0	0	0
T7	3836	24	0	0
T8	6694	31	0	0
T9	134726	0	0	0
T10	198251	0	0	0
T14	0	840	0	0
T17	0	1436	0	0
T18	0	580	0	0
T21	0	152	0	0
T24	0	497	0	0
T25	0	21	0	0
T35	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	463766	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	463766	0	0
T1	339680	1400	0	0
T2	157669	0	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	0	0	0
T6	1082	0	0	0
T7	3836	24	0	0
T8	6694	31	0	0
T9	134726	0	0	0
T10	198251	0	0	0
T14	0	840	0	0
T17	0	1436	0	0
T18	0	2519	0	0
T21	0	721	0	0
T24	0	497	0	0
T25	0	21	0	0
T35	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	6619866	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	6619866	0	0
T1	339680	5470	0	0
T2	157669	5190	0	0
T3	5378	235	0	0
T4	1165	3	0	0
T5	124525	69	0	0
T6	1082	13	0	0
T7	3836	221	0	0
T8	6694	709	0	0
T9	134726	54	0	0
T10	198251	8016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488229345	14082383	0	0
DepthKnown_A	488229345	488095217	0	0
RvalidKnown_A	488229345	488095217	0	0
WreadyKnown_A	488229345	488095217	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	14082383	0	0
T1	339680	23246	0	0
T2	157669	16020	0	0
T3	5378	235	0	0
T4	1165	9	0	0
T5	124525	149	0	0
T6	1082	13	0	0
T7	3836	221	0	0
T8	6694	709	0	0
T9	134726	54	0	0
T10	198251	8016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488229345	488095217	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0