Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Covered	T1,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T21
1	0	Covered	T17,T18,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Unreachable
1	1	Covered	T17,T18,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	784559973	633828283	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	784559973	3908549	0	0
GntImpliesValid_A	784559973	3908549	0	0
GrantKnown_A	784559973	633828283	0	0
IdxKnown_A	784559973	633828283	0	0
IndexIsCorrect_A	784559973	3908549	0	0
LockArbDecision_A	784559973	0	0	0
NoReadyValidNoGrant_A	784559973	0	0	0
ReadyAndValidImplyGrant_A	784559973	3908549	0	0
ReqAndReadyImplyGrant_A	784559973	3908549	0	0
ReqImpliesValid_A	784559973	3908549	0	0
ReqStaysHighUntilGranted0_M	784559973	0	0	0
RoundRobin_A	784559973	5	0	956
ValidKnown_A	784559973	633828283	0	0
gen_data_port_assertion.DataFlow_A	784559973	3908549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	633828283	0	0
T1	380898	377750	0	0
T2	208977	183223	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	609773	367072	0	0
T6	1082	1021	0	0
T7	7644	5451	0	0
T8	11214	8533	0	0
T9	266310	200453	0	0
T10	261891	230020	0	0
T11	144	72	0	0
T12	223452	105208	0	0
T14	818978	403264	0	0
T16	5914	5914	0	0
T17	0	704393	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	633828283	0	0
T1	380898	377750	0	0
T2	208977	183223	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	609773	367072	0	0
T6	1082	1021	0	0
T7	7644	5451	0	0
T8	11214	8533	0	0
T9	266310	200453	0	0
T10	261891	230020	0	0
T11	144	72	0	0
T12	223452	105208	0	0
T14	818978	403264	0	0
T16	5914	5914	0	0
T17	0	704393	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	633828283	0	0
T1	380898	377750	0	0
T2	208977	183223	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	609773	367072	0	0
T6	1082	1021	0	0
T7	7644	5451	0	0
T8	11214	8533	0	0
T9	266310	200453	0	0
T10	261891	230020	0	0
T11	144	72	0	0
T12	223452	105208	0	0
T14	818978	403264	0	0
T16	5914	5914	0	0
T17	0	704393	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	5	0	956
T47	832071	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	129047	0	0	1
T53	656159	0	0	1
T54	334158	0	0	1
T55	39346	0	0	1
T56	28976	0	0	1
T57	5699	0	0	1
T58	321463	0	0	1
T59	812	0	0	1
T60	10515	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	633828283	0	0
T1	380898	377750	0	0
T2	208977	183223	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	609773	367072	0	0
T6	1082	1021	0	0
T7	7644	5451	0	0
T8	11214	8533	0	0
T9	266310	200453	0	0
T10	261891	230020	0	0
T11	144	72	0	0
T12	223452	105208	0	0
T14	818978	403264	0	0
T16	5914	5914	0	0
T17	0	704393	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784559973	3908549	0	0
T1	380898	2687	0	0
T2	183323	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	367149	832	0	0
T6	1082	0	0	0
T7	5740	139	0	0
T8	8954	186	0	0
T9	200518	832	0	0
T10	230071	1344	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	7251	0	0
T16	0	832	0	0
T17	711808	10285	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	10402	0	0
T24	76777	3138	0	0
T25	2400	121	0	0
T27	0	1704	0	0
T35	0	1032	0	0
T37	0	832	0	0
T38	106434	0	0	0
T39	0	10	0	0
T45	0	4161	0	0
T46	0	5480	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Covered	T1,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149232831	29172151	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149232831	659198	0	0
GntImpliesValid_A	149232831	659198	0	0
GrantKnown_A	149232831	29172151	0	0
IdxKnown_A	149232831	29172151	0	0
IndexIsCorrect_A	149232831	659198	0	0
LockArbDecision_A	149232831	0	0	0
NoReadyValidNoGrant_A	149232831	0	0	0
ReadyAndValidImplyGrant_A	149232831	659198	0	0
ReqAndReadyImplyGrant_A	149232831	659198	0	0
ReqImpliesValid_A	149232831	659198	0	0
ReqStaysHighUntilGranted0_M	149232831	0	0	0
RoundRobin_A	149232831	0	0	0
ValidKnown_A	149232831	29172151	0	0
gen_data_port_assertion.DataFlow_A	149232831	659198	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	29172151	0	0
T1	41218	38120	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	1712	0	0
T8	2260	1896	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	72	0	0
T12	111726	105208	0	0
T14	409489	403264	0	0
T17	0	149328	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	29172151	0	0
T1	41218	38120	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	1712	0	0
T8	2260	1896	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	72	0	0
T12	111726	105208	0	0
T14	409489	403264	0	0
T17	0	149328	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	29172151	0	0
T1	41218	38120	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	1712	0	0
T8	2260	1896	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	72	0	0
T12	111726	105208	0	0
T14	409489	403264	0	0
T17	0	149328	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	29172151	0	0
T1	41218	38120	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	1712	0	0
T8	2260	1896	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	72	0	0
T12	111726	105208	0	0
T14	409489	403264	0	0
T17	0	149328	0	0
T24	0	73632	0	0
T25	0	2400	0	0
T26	0	1008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	659198	0	0
T1	41218	1847	0	0
T2	25654	0	0	0
T5	242624	0	0	0
T7	1904	106	0	0
T8	2260	137	0	0
T9	65792	0	0	0
T10	31820	0	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	4884	0	0
T17	0	6804	0	0
T23	0	1248	0	0
T24	0	3138	0	0
T25	0	121	0	0
T27	0	1704	0	0
T45	0	4159	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T21
1	0	Covered	T17,T18,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Unreachable
1	1	Covered	T17,T18,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T21
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149232831	118650237	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149232831	947623	0	0
GntImpliesValid_A	149232831	947623	0	0
GrantKnown_A	149232831	118650237	0	0
IdxKnown_A	149232831	118650237	0	0
IndexIsCorrect_A	149232831	947623	0	0
LockArbDecision_A	149232831	0	0	0
NoReadyValidNoGrant_A	149232831	0	0	0
ReadyAndValidImplyGrant_A	149232831	947623	0	0
ReqAndReadyImplyGrant_A	149232831	947623	0	0
ReqImpliesValid_A	149232831	947623	0	0
ReqStaysHighUntilGranted0_M	149232831	0	0	0
RoundRobin_A	149232831	0	0	0
ValidKnown_A	149232831	118650237	0	0
gen_data_port_assertion.DataFlow_A	149232831	947623	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	118650237	0	0
T2	25654	25654	0	0
T5	242624	242624	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	65792	0	0
T10	31820	31820	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	5914	0	0
T17	0	555065	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T21	0	282875	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	118650237	0	0
T2	25654	25654	0	0
T5	242624	242624	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	65792	0	0
T10	31820	31820	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	5914	0	0
T17	0	555065	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T21	0	282875	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	118650237	0	0
T2	25654	25654	0	0
T5	242624	242624	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	65792	0	0
T10	31820	31820	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	5914	0	0
T17	0	555065	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T21	0	282875	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	118650237	0	0
T2	25654	25654	0	0
T5	242624	242624	0	0
T7	1904	0	0	0
T8	2260	0	0	0
T9	65792	65792	0	0
T10	31820	31820	0	0
T11	72	0	0	0
T12	111726	0	0	0
T14	409489	0	0	0
T16	5914	5914	0	0
T17	0	555065	0	0
T18	0	102499	0	0
T19	0	50092	0	0
T20	0	171954	0	0
T21	0	282875	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149232831	947623	0	0
T17	711808	3481	0	0
T18	102788	10395	0	0
T19	50396	0	0	0
T20	172406	0	0	0
T21	285907	2736	0	0
T23	0	9154	0	0
T24	76777	0	0	0
T25	2400	0	0	0
T28	0	5362	0	0
T35	0	1032	0	0
T38	106434	0	0	0
T39	115517	10	0	0
T40	45986	0	0	0
T41	0	9715	0	0
T45	0	2	0	0
T46	0	5480	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	486094311	486005895	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	486094311	2301728	0	0
GntImpliesValid_A	486094311	2301728	0	0
GrantKnown_A	486094311	486005895	0	0
IdxKnown_A	486094311	486005895	0	0
IndexIsCorrect_A	486094311	2301728	0	0
LockArbDecision_A	486094311	0	0	0
NoReadyValidNoGrant_A	486094311	0	0	0
ReadyAndValidImplyGrant_A	486094311	2301728	0	0
ReqAndReadyImplyGrant_A	486094311	2301728	0	0
ReqImpliesValid_A	486094311	2301728	0	0
ReqStaysHighUntilGranted0_M	486094311	0	0	0
RoundRobin_A	486094311	5	0	956
ValidKnown_A	486094311	486005895	0	0
gen_data_port_assertion.DataFlow_A	486094311	2301728	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	486005895	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	486005895	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	486005895	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	5	0	956
T47	832071	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	129047	0	0	1
T53	656159	0	0	1
T54	334158	0	0	1
T55	39346	0	0	1
T56	28976	0	0	1
T57	5699	0	0	1
T58	321463	0	0	1
T59	812	0	0	1
T60	10515	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	486005895	0	0
T1	339680	339630	0	0
T2	157669	157569	0	0
T3	5378	5023	0	0
T4	1165	1065	0	0
T5	124525	124448	0	0
T6	1082	1021	0	0
T7	3836	3739	0	0
T8	6694	6637	0	0
T9	134726	134661	0	0
T10	198251	198200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486094311	2301728	0	0
T1	339680	840	0	0
T2	157669	832	0	0
T3	5378	0	0	0
T4	1165	0	0	0
T5	124525	832	0	0
T6	1082	0	0	0
T7	3836	33	0	0
T8	6694	49	0	0
T9	134726	832	0	0
T10	198251	1344	0	0
T14	0	2367	0	0
T16	0	832	0	0
T37	0	832	0	0