Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3647111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4234213

1

T1

96

T2

10698

T3

11578

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4264728	1			T1	7526		T2	13687		T3	21457
values[0x0]	1808650	1			T1	43		T2	5516		T3	5977
values[0x1]	1807946	1			T1	40		T2	5424		T3	6022

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2575841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5305483

1

T1

2555

T2

15149

T3

18623

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33988	1			T1	36		T2	86		T3	142
valid_sources[0x01]	34423	1			T1	33		T2	83		T3	121
valid_sources[0x02]	37420	1			T1	30		T2	98		T3	123
valid_sources[0x03]	26670	1			T1	21		T2	104		T3	141
valid_sources[0x04]	27556	1			T1	30		T2	84		T3	123
valid_sources[0x05]	29664	1			T1	33		T2	83		T3	115
valid_sources[0x06]	28356	1			T1	28		T2	87		T3	129
valid_sources[0x07]	28301	1			T1	28		T2	97		T3	137
valid_sources[0x08]	29983	1			T1	26		T2	121		T3	130
valid_sources[0x09]	29470	1			T1	27		T2	88		T3	133
valid_sources[0x0a]	32295	1			T1	33		T2	110		T3	143
valid_sources[0x0b]	28822	1			T1	34		T2	107		T3	123
valid_sources[0x0c]	26679	1			T1	28		T2	97		T3	141
valid_sources[0x0d]	28546	1			T1	27		T2	100		T3	132
valid_sources[0x0e]	35943	1			T1	22		T2	101		T3	113
valid_sources[0x0f]	29833	1			T1	30		T2	110		T3	132
valid_sources[0x10]	28785	1			T1	35		T2	104		T3	140
valid_sources[0x11]	30731	1			T1	32		T2	127		T3	106
valid_sources[0x12]	28222	1			T1	23		T2	101		T3	138
valid_sources[0x13]	32932	1			T1	22		T2	105		T3	141
valid_sources[0x14]	28684	1			T1	31		T2	98		T3	125
valid_sources[0x15]	31934	1			T1	22		T2	83		T3	125
valid_sources[0x16]	36545	1			T1	37		T2	93		T3	116
valid_sources[0x17]	48562	1			T1	27		T2	122		T3	133
valid_sources[0x18]	29633	1			T1	34		T2	99		T3	137
valid_sources[0x19]	54340	1			T1	28		T2	95		T3	141
valid_sources[0x1a]	27852	1			T1	27		T2	96		T3	123
valid_sources[0x1b]	28282	1			T1	20		T2	95		T3	136
valid_sources[0x1c]	28314	1			T1	31		T2	87		T3	141
valid_sources[0x1d]	29566	1			T1	28		T2	136		T3	114
valid_sources[0x1e]	31969	1			T1	35		T2	69		T3	128
valid_sources[0x1f]	28246	1			T1	30		T2	127		T3	146
valid_sources[0x20]	27786	1			T1	30		T2	104		T3	122
valid_sources[0x21]	28476	1			T1	28		T2	106		T3	148
valid_sources[0x22]	28145	1			T1	30		T2	116		T3	137
valid_sources[0x23]	27302	1			T1	35		T2	90		T3	148
valid_sources[0x24]	29703	1			T1	43		T2	122		T3	120
valid_sources[0x25]	30657	1			T1	32		T2	76		T3	110
valid_sources[0x26]	29797	1			T1	21		T2	90		T3	119
valid_sources[0x27]	30532	1			T1	24		T2	108		T3	129
valid_sources[0x28]	29994	1			T1	33		T2	91		T3	139
valid_sources[0x29]	30450	1			T1	36		T2	92		T3	133
valid_sources[0x2a]	32641	1			T1	31		T2	104		T3	130
valid_sources[0x2b]	27725	1			T1	36		T2	109		T3	125
valid_sources[0x2c]	37740	1			T1	27		T2	112		T3	132
valid_sources[0x2d]	30738	1			T1	31		T2	121		T3	129
valid_sources[0x2e]	29852	1			T1	29		T2	75		T3	148
valid_sources[0x2f]	81838	1			T1	31		T2	89		T3	142
valid_sources[0x30]	27854	1			T1	28		T2	107		T3	110
valid_sources[0x31]	38499	1			T1	26		T2	76		T3	143
valid_sources[0x32]	30402	1			T1	27		T2	102		T3	145
valid_sources[0x33]	28731	1			T1	31		T2	96		T3	93
valid_sources[0x34]	28742	1			T1	29		T2	110		T3	130
valid_sources[0x35]	30327	1			T1	29		T2	101		T3	129
valid_sources[0x36]	35304	1			T1	29		T2	94		T3	133
valid_sources[0x37]	29049	1			T1	33		T2	87		T3	127
valid_sources[0x38]	34183	1			T1	36		T2	85		T3	125
valid_sources[0x39]	29406	1			T1	26		T2	114		T3	133
valid_sources[0x3a]	29907	1			T1	41		T2	86		T3	131
valid_sources[0x3b]	30608	1			T1	31		T2	97		T3	129
valid_sources[0x3c]	38120	1			T1	30		T2	112		T3	128
valid_sources[0x3d]	29471	1			T1	30		T2	94		T3	145
valid_sources[0x3e]	31334	1			T1	43		T2	79		T3	128
valid_sources[0x3f]	29860	1			T1	25		T2	71		T3	147
valid_sources[0x40]	26887	1			T1	34		T2	108		T3	141
valid_sources[0x41]	29094	1			T1	36		T2	120		T3	128
valid_sources[0x42]	33958	1			T1	22		T2	89		T3	120
valid_sources[0x43]	29922	1			T1	20		T2	98		T3	144
valid_sources[0x44]	27991	1			T1	37		T2	83		T3	114
valid_sources[0x45]	27524	1			T1	32		T2	106		T3	152
valid_sources[0x46]	32607	1			T1	23		T2	109		T3	119
valid_sources[0x47]	27620	1			T1	29		T2	97		T3	132
valid_sources[0x48]	29461	1			T1	35		T2	93		T3	143
valid_sources[0x49]	28824	1			T1	31		T2	107		T3	152
valid_sources[0x4a]	29315	1			T1	28		T2	91		T3	145
valid_sources[0x4b]	28193	1			T1	32		T2	89		T3	122
valid_sources[0x4c]	35614	1			T1	31		T2	116		T3	125
valid_sources[0x4d]	27635	1			T1	30		T2	114		T3	135
valid_sources[0x4e]	36614	1			T1	31		T2	113		T3	123
valid_sources[0x4f]	29414	1			T1	25		T2	103		T3	128
valid_sources[0x50]	29027	1			T1	29		T2	88		T3	126
valid_sources[0x51]	33639	1			T1	25		T2	97		T3	132
valid_sources[0x52]	32176	1			T1	29		T2	71		T3	105
valid_sources[0x53]	27082	1			T1	27		T2	100		T3	129
valid_sources[0x54]	28293	1			T1	34		T2	95		T3	125
valid_sources[0x55]	26843	1			T1	26		T2	103		T3	125
valid_sources[0x56]	27483	1			T1	32		T2	99		T3	123
valid_sources[0x57]	35514	1			T1	28		T2	99		T3	129
valid_sources[0x58]	28025	1			T1	34		T2	89		T3	141
valid_sources[0x59]	31691	1			T1	40		T2	81		T3	126
valid_sources[0x5a]	30544	1			T1	28		T2	75		T3	121
valid_sources[0x5b]	42190	1			T1	35		T2	89		T3	106
valid_sources[0x5c]	29328	1			T1	35		T2	87		T3	143
valid_sources[0x5d]	29765	1			T1	24		T2	95		T3	105
valid_sources[0x5e]	26989	1			T1	27		T2	105		T3	144
valid_sources[0x5f]	31332	1			T1	30		T2	109		T3	114
valid_sources[0x60]	30669	1			T1	25		T2	106		T3	118
valid_sources[0x61]	27870	1			T1	40		T2	128		T3	143
valid_sources[0x62]	29693	1			T1	31		T2	83		T3	135
valid_sources[0x63]	30173	1			T1	27		T2	88		T3	128
valid_sources[0x64]	50729	1			T1	32		T2	110		T3	136
valid_sources[0x65]	27907	1			T1	20		T2	102		T3	133
valid_sources[0x66]	31727	1			T1	34		T2	131		T3	123
valid_sources[0x67]	28250	1			T1	30		T2	95		T3	133
valid_sources[0x68]	27884	1			T1	31		T2	102		T3	120
valid_sources[0x69]	30974	1			T1	31		T2	87		T3	147
valid_sources[0x6a]	31895	1			T1	37		T2	109		T3	132
valid_sources[0x6b]	47391	1			T1	31		T2	112		T3	135
valid_sources[0x6c]	26997	1			T1	36		T2	87		T3	134
valid_sources[0x6d]	34031	1			T1	26		T2	114		T3	118
valid_sources[0x6e]	32992	1			T1	39		T2	103		T3	124
valid_sources[0x6f]	27633	1			T1	24		T2	105		T3	144
valid_sources[0x70]	33283	1			T1	38		T2	97		T3	117
valid_sources[0x71]	31966	1			T1	29		T2	85		T3	125
valid_sources[0x72]	33412	1			T1	22		T2	101		T3	126
valid_sources[0x73]	27465	1			T1	29		T2	76		T3	147
valid_sources[0x74]	29515	1			T1	26		T2	106		T3	137
valid_sources[0x75]	37123	1			T1	34		T2	83		T3	132
valid_sources[0x76]	27201	1			T1	29		T2	93		T3	136
valid_sources[0x77]	29470	1			T1	31		T2	81		T3	117
valid_sources[0x78]	27652	1			T1	20		T2	80		T3	119
valid_sources[0x79]	27343	1			T1	26		T2	113		T3	123
valid_sources[0x7a]	31838	1			T1	35		T2	71		T3	126
valid_sources[0x7b]	26499	1			T1	44		T2	116		T3	118
valid_sources[0x7c]	28201	1			T1	31		T2	70		T3	138
valid_sources[0x7d]	30238	1			T1	25		T2	100		T3	123
valid_sources[0x7e]	31875	1			T1	42		T2	118		T3	146
valid_sources[0x7f]	29361	1			T1	24		T2	99		T3	145
valid_sources[0x80]	29578	1			T1	30		T2	76		T3	143

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

962764

1

T1

51

T2

1171

T3

1669

values[0x0]

all_enables

biggest_size

1648762

1

T1

27

T2

4855

T3

5017

values[0x1]

all_enables

biggest_size

1622687

1

T1

18

T2

4672

T3

4892