Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3666120

1

T1

7513

T2

13929

T3

21878

full_word

4235327

1

T1

96

T2

10698

T3

11578

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7901047	1			T1	7609		T2	24627		T3	33456
auto[TlIntgErrCmd]	136	1			T59	13		T60	6		T61	9
auto[TlIntgErrData]	119	1			T59	10		T60	1		T61	10
auto[TlIntgErrBoth]	145	1			T59	7		T60	13		T61	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4267763

1

T1

7526

T2

13687

T3

21457

auto[1]

3633684

1

T1

83

T2

10940

T3

11999

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3304572	1			T1	7475		T2	12516		T3	19788
auto[TlIntgErrNone]	partial	auto[1]	361179	1			T1	38		T2	1413		T3	2090
auto[TlIntgErrNone]	full_word	auto[0]	963012	1			T1	51		T2	1171		T3	1669
auto[TlIntgErrNone]	full_word	auto[1]	3272284	1			T1	45		T2	9527		T3	9909
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T59	4		T60	3		T61	5
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T59	9		T60	3		T61	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T110	1		T165	3		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T61	1		T166	1		T167	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T59	4		T61	5		T109	7
auto[TlIntgErrData]	partial	auto[1]	54	1			T59	5		T60	1		T61	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T110	1		T167	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T59	1		T167	1		T98	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T59	2		T60	7		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T59	4		T60	6		T61	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T61	1		T109	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T59	1		T61	2		T165	2