Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	750090424	600713896	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	750090424	3703191	0	0
GntImpliesValid_A	750090424	3703191	0	0
GrantKnown_A	750090424	600713896	0	0
IdxKnown_A	750090424	600713896	0	0
IndexIsCorrect_A	750090424	3703191	0	0
LockArbDecision_A	750090424	0	0	0
NoReadyValidNoGrant_A	750090424	0	0	0
ReadyAndValidImplyGrant_A	750090424	3703191	0	0
ReqAndReadyImplyGrant_A	750090424	3703191	0	0
ReqImpliesValid_A	750090424	3703191	0	0
ReqStaysHighUntilGranted0_M	750090424	0	0	0
RoundRobin_A	750090424	5	0	956
ValidKnown_A	750090424	600713896	0	0
gen_data_port_assertion.DataFlow_A	750090424	3703191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	600713896	0	0
T1	24985	24785	0	0
T2	483055	294231	0	0
T3	673826	422780	0	0
T4	747186	654657	0	0
T5	56626	44805	0	0
T6	31143	19845	0	0
T7	85206	51560	0	0
T8	140851	126440	0	0
T9	1728	1654	0	0
T10	5517	5008	0	0
T11	21396	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	600713896	0	0
T1	24985	24785	0	0
T2	483055	294231	0	0
T3	673826	422780	0	0
T4	747186	654657	0	0
T5	56626	44805	0	0
T6	31143	19845	0	0
T7	85206	51560	0	0
T8	140851	126440	0	0
T9	1728	1654	0	0
T10	5517	5008	0	0
T11	21396	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	600713896	0	0
T1	24985	24785	0	0
T2	483055	294231	0	0
T3	673826	422780	0	0
T4	747186	654657	0	0
T5	56626	44805	0	0
T6	31143	19845	0	0
T7	85206	51560	0	0
T8	140851	126440	0	0
T9	1728	1654	0	0
T10	5517	5008	0	0
T11	21396	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	5	0	956
T15	633878	1	0	1
T41	322466	0	0	1
T42	174570	0	0	1
T46	279915	0	0	1
T47	159123	0	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	190754	0	0	1
T53	12081	0	0	1
T54	19557	0	0	1
T55	41808	0	0	1
T56	51359	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	600713896	0	0
T1	24985	24785	0	0
T2	483055	294231	0	0
T3	673826	422780	0	0
T4	747186	654657	0	0
T5	56626	44805	0	0
T6	31143	19845	0	0
T7	85206	51560	0	0
T8	140851	126440	0	0
T9	1728	1654	0	0
T10	5517	5008	0	0
T11	21396	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750090424	3703191	0	0
T1	24985	258	0	0
T2	483055	7529	0	0
T3	673826	6651	0	0
T4	747186	1344	0	0
T5	56626	832	0	0
T6	31143	1344	0	0
T7	85206	832	0	0
T8	140851	832	0	0
T9	1728	0	0	0
T10	5517	0	0	0
T11	21396	832	0	0
T12	588581	12007	0	0
T13	0	3582	0	0
T14	0	2045	0	0
T15	0	14185	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	1785	0	0
T30	0	3003	0	0
T41	0	317	0	0
T45	0	240	0	0
T46	0	1671	0	0
T47	0	1814	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147942076	26690281	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147942076	636771	0	0
GntImpliesValid_A	147942076	636771	0	0
GrantKnown_A	147942076	26690281	0	0
IdxKnown_A	147942076	26690281	0	0
IndexIsCorrect_A	147942076	636771	0	0
LockArbDecision_A	147942076	0	0	0
NoReadyValidNoGrant_A	147942076	0	0	0
ReadyAndValidImplyGrant_A	147942076	636771	0	0
ReqAndReadyImplyGrant_A	147942076	636771	0	0
ReqImpliesValid_A	147942076	636771	0	0
ReqStaysHighUntilGranted0_M	147942076	0	0	0
RoundRobin_A	147942076	0	0	0
ValidKnown_A	147942076	26690281	0	0
gen_data_port_assertion.DataFlow_A	147942076	636771	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	26690281	0	0
T1	2721	2616	0	0
T2	185547	49288	0	0
T3	249156	42016	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	432	0	0
T11	10698	0	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	26690281	0	0
T1	2721	2616	0	0
T2	185547	49288	0	0
T3	249156	42016	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	432	0	0
T11	10698	0	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	26690281	0	0
T1	2721	2616	0	0
T2	185547	49288	0	0
T3	249156	42016	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	432	0	0
T11	10698	0	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	26690281	0	0
T1	2721	2616	0	0
T2	185547	49288	0	0
T3	249156	42016	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	432	0	0
T11	10698	0	0	0
T14	0	113296	0	0
T24	0	26048	0	0
T25	0	432	0	0
T26	0	27888	0	0
T29	0	89768	0	0
T30	0	64752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	636771	0	0
T1	2721	191	0	0
T2	185547	1836	0	0
T3	249156	2030	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T14	0	1312	0	0
T15	0	8648	0	0
T24	0	522	0	0
T25	0	44	0	0
T26	0	987	0	0
T30	0	3003	0	0
T45	0	240	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147942076	119905277	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147942076	773147	0	0
GntImpliesValid_A	147942076	773147	0	0
GrantKnown_A	147942076	119905277	0	0
IdxKnown_A	147942076	119905277	0	0
IndexIsCorrect_A	147942076	773147	0	0
LockArbDecision_A	147942076	0	0	0
NoReadyValidNoGrant_A	147942076	0	0	0
ReadyAndValidImplyGrant_A	147942076	773147	0	0
ReqAndReadyImplyGrant_A	147942076	773147	0	0
ReqImpliesValid_A	147942076	773147	0	0
ReqStaysHighUntilGranted0_M	147942076	0	0	0
RoundRobin_A	147942076	0	0	0
ValidKnown_A	147942076	119905277	0	0
gen_data_port_assertion.DataFlow_A	147942076	773147	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	119905277	0	0
T2	185547	132988	0	0
T3	249156	205259	0	0
T4	92446	92446	0	0
T5	11284	10820	0	0
T6	11244	11244	0	0
T7	33456	33344	0	0
T8	14005	13656	0	0
T10	432	0	0	0
T11	10698	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	119905277	0	0
T2	185547	132988	0	0
T3	249156	205259	0	0
T4	92446	92446	0	0
T5	11284	10820	0	0
T6	11244	11244	0	0
T7	33456	33344	0	0
T8	14005	13656	0	0
T10	432	0	0	0
T11	10698	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	119905277	0	0
T2	185547	132988	0	0
T3	249156	205259	0	0
T4	92446	92446	0	0
T5	11284	10820	0	0
T6	11244	11244	0	0
T7	33456	33344	0	0
T8	14005	13656	0	0
T10	432	0	0	0
T11	10698	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	119905277	0	0
T2	185547	132988	0	0
T3	249156	205259	0	0
T4	92446	92446	0	0
T5	11284	10820	0	0
T6	11244	11244	0	0
T7	33456	33344	0	0
T8	14005	13656	0	0
T10	432	0	0	0
T11	10698	10400	0	0
T12	588581	587050	0	0
T13	0	133508	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147942076	773147	0	0
T2	185547	521	0	0
T3	249156	1980	0	0
T4	92446	0	0	0
T5	11284	0	0	0
T6	11244	0	0	0
T7	33456	0	0	0
T8	14005	0	0	0
T10	432	0	0	0
T11	10698	0	0	0
T12	588581	4309	0	0
T13	0	3582	0	0
T14	0	733	0	0
T15	0	5537	0	0
T26	0	798	0	0
T41	0	317	0	0
T46	0	1671	0	0
T47	0	1814	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	454206272	454118338	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	454206272	2293273	0	0
GntImpliesValid_A	454206272	2293273	0	0
GrantKnown_A	454206272	454118338	0	0
IdxKnown_A	454206272	454118338	0	0
IndexIsCorrect_A	454206272	2293273	0	0
LockArbDecision_A	454206272	0	0	0
NoReadyValidNoGrant_A	454206272	0	0	0
ReadyAndValidImplyGrant_A	454206272	2293273	0	0
ReqAndReadyImplyGrant_A	454206272	2293273	0	0
ReqImpliesValid_A	454206272	2293273	0	0
ReqStaysHighUntilGranted0_M	454206272	0	0	0
RoundRobin_A	454206272	5	0	956
ValidKnown_A	454206272	454118338	0	0
gen_data_port_assertion.DataFlow_A	454206272	2293273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	454118338	0	0
T1	22264	22169	0	0
T2	111961	111955	0	0
T3	175514	175505	0	0
T4	562294	562211	0	0
T5	34058	33985	0	0
T6	8655	8601	0	0
T7	18294	18216	0	0
T8	112841	112784	0	0
T9	1728	1654	0	0
T10	4653	4576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	454118338	0	0
T1	22264	22169	0	0
T2	111961	111955	0	0
T3	175514	175505	0	0
T4	562294	562211	0	0
T5	34058	33985	0	0
T6	8655	8601	0	0
T7	18294	18216	0	0
T8	112841	112784	0	0
T9	1728	1654	0	0
T10	4653	4576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	454118338	0	0
T1	22264	22169	0	0
T2	111961	111955	0	0
T3	175514	175505	0	0
T4	562294	562211	0	0
T5	34058	33985	0	0
T6	8655	8601	0	0
T7	18294	18216	0	0
T8	112841	112784	0	0
T9	1728	1654	0	0
T10	4653	4576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	5	0	956
T15	633878	1	0	1
T41	322466	0	0	1
T42	174570	0	0	1
T46	279915	0	0	1
T47	159123	0	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	190754	0	0	1
T53	12081	0	0	1
T54	19557	0	0	1
T55	41808	0	0	1
T56	51359	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	454118338	0	0
T1	22264	22169	0	0
T2	111961	111955	0	0
T3	175514	175505	0	0
T4	562294	562211	0	0
T5	34058	33985	0	0
T6	8655	8601	0	0
T7	18294	18216	0	0
T8	112841	112784	0	0
T9	1728	1654	0	0
T10	4653	4576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454206272	2293273	0	0
T1	22264	67	0	0
T2	111961	5172	0	0
T3	175514	2641	0	0
T4	562294	1344	0	0
T5	34058	832	0	0
T6	8655	1344	0	0
T7	18294	832	0	0
T8	112841	832	0	0
T9	1728	0	0	0
T10	4653	0	0	0
T11	0	832	0	0
T12	0	7698	0	0