Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3721 |
0 |
0 |
T59 |
28221 |
1 |
0 |
0 |
T60 |
18526 |
3 |
0 |
0 |
T61 |
28427 |
4 |
0 |
0 |
T86 |
5971 |
361 |
0 |
0 |
T87 |
4268 |
9 |
0 |
0 |
T88 |
11673 |
8 |
0 |
0 |
T89 |
4211 |
2 |
0 |
0 |
T90 |
2891 |
158 |
0 |
0 |
T109 |
82738 |
4 |
0 |
0 |
T110 |
35552 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
656 |
0 |
0 |
T102 |
16176 |
27 |
0 |
0 |
T110 |
35552 |
39 |
0 |
0 |
T114 |
7741 |
1 |
0 |
0 |
T119 |
7535 |
6 |
0 |
0 |
T136 |
12725 |
3 |
0 |
0 |
T137 |
78677 |
156 |
0 |
0 |
T138 |
14506 |
5 |
0 |
0 |
T139 |
19422 |
50 |
0 |
0 |
T140 |
13712 |
9 |
0 |
0 |
T141 |
4787 |
2 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
673 |
0 |
0 |
T102 |
16176 |
27 |
0 |
0 |
T110 |
35552 |
20 |
0 |
0 |
T114 |
7741 |
6 |
0 |
0 |
T119 |
7535 |
5 |
0 |
0 |
T136 |
12725 |
18 |
0 |
0 |
T137 |
78677 |
124 |
0 |
0 |
T138 |
14506 |
21 |
0 |
0 |
T139 |
19422 |
41 |
0 |
0 |
T140 |
13712 |
10 |
0 |
0 |
T142 |
6615 |
8 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
934 |
0 |
0 |
T102 |
16176 |
16 |
0 |
0 |
T110 |
35552 |
90 |
0 |
0 |
T114 |
7741 |
1 |
0 |
0 |
T119 |
7535 |
24 |
0 |
0 |
T136 |
12725 |
10 |
0 |
0 |
T137 |
78677 |
146 |
0 |
0 |
T138 |
14506 |
4 |
0 |
0 |
T139 |
19422 |
37 |
0 |
0 |
T140 |
13712 |
12 |
0 |
0 |
T141 |
4787 |
19 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
4218 |
0 |
0 |
T102 |
16176 |
347 |
0 |
0 |
T110 |
35552 |
1038 |
0 |
0 |
T114 |
7741 |
142 |
0 |
0 |
T119 |
7535 |
9 |
0 |
0 |
T136 |
12725 |
39 |
0 |
0 |
T137 |
78677 |
159 |
0 |
0 |
T138 |
14506 |
59 |
0 |
0 |
T139 |
19422 |
68 |
0 |
0 |
T140 |
13712 |
21 |
0 |
0 |
T142 |
6615 |
1 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3557 |
0 |
0 |
T102 |
16176 |
289 |
0 |
0 |
T110 |
35552 |
547 |
0 |
0 |
T114 |
7741 |
49 |
0 |
0 |
T119 |
7535 |
138 |
0 |
0 |
T136 |
12725 |
57 |
0 |
0 |
T137 |
78677 |
158 |
0 |
0 |
T138 |
14506 |
150 |
0 |
0 |
T139 |
19422 |
32 |
0 |
0 |
T140 |
13712 |
32 |
0 |
0 |
T142 |
6615 |
15 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
2989 |
0 |
0 |
T102 |
16176 |
143 |
0 |
0 |
T110 |
35552 |
657 |
0 |
0 |
T114 |
7741 |
5 |
0 |
0 |
T119 |
7535 |
154 |
0 |
0 |
T136 |
12725 |
11 |
0 |
0 |
T137 |
78677 |
172 |
0 |
0 |
T138 |
14506 |
42 |
0 |
0 |
T139 |
19422 |
65 |
0 |
0 |
T140 |
13712 |
31 |
0 |
0 |
T142 |
6615 |
6 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3683 |
0 |
0 |
T102 |
16176 |
277 |
0 |
0 |
T110 |
35552 |
505 |
0 |
0 |
T114 |
7741 |
79 |
0 |
0 |
T119 |
7535 |
10 |
0 |
0 |
T136 |
12725 |
23 |
0 |
0 |
T137 |
78677 |
119 |
0 |
0 |
T138 |
14506 |
213 |
0 |
0 |
T139 |
19422 |
42 |
0 |
0 |
T140 |
13712 |
46 |
0 |
0 |
T141 |
4787 |
109 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3729 |
0 |
0 |
T102 |
16176 |
282 |
0 |
0 |
T110 |
35552 |
344 |
0 |
0 |
T114 |
7741 |
60 |
0 |
0 |
T119 |
7535 |
215 |
0 |
0 |
T136 |
12725 |
36 |
0 |
0 |
T137 |
78677 |
152 |
0 |
0 |
T138 |
14506 |
23 |
0 |
0 |
T139 |
19422 |
55 |
0 |
0 |
T140 |
13712 |
39 |
0 |
0 |
T142 |
6615 |
8 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3170 |
0 |
0 |
T102 |
16176 |
119 |
0 |
0 |
T110 |
35552 |
286 |
0 |
0 |
T114 |
7741 |
82 |
0 |
0 |
T119 |
7535 |
136 |
0 |
0 |
T136 |
12725 |
54 |
0 |
0 |
T137 |
78677 |
109 |
0 |
0 |
T138 |
14506 |
62 |
0 |
0 |
T139 |
19422 |
33 |
0 |
0 |
T140 |
13712 |
24 |
0 |
0 |
T142 |
6615 |
15 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3371 |
0 |
0 |
T102 |
16176 |
317 |
0 |
0 |
T110 |
35552 |
350 |
0 |
0 |
T114 |
7741 |
98 |
0 |
0 |
T119 |
7535 |
151 |
0 |
0 |
T136 |
12725 |
23 |
0 |
0 |
T137 |
78677 |
119 |
0 |
0 |
T138 |
14506 |
177 |
0 |
0 |
T139 |
19422 |
44 |
0 |
0 |
T140 |
13712 |
30 |
0 |
0 |
T142 |
6615 |
12 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
3620 |
0 |
0 |
T102 |
16176 |
301 |
0 |
0 |
T110 |
35552 |
296 |
0 |
0 |
T114 |
7741 |
47 |
0 |
0 |
T119 |
7535 |
146 |
0 |
0 |
T136 |
12725 |
21 |
0 |
0 |
T137 |
78677 |
118 |
0 |
0 |
T138 |
14506 |
227 |
0 |
0 |
T139 |
19422 |
26 |
0 |
0 |
T140 |
13712 |
59 |
0 |
0 |
T142 |
6615 |
4 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1885 |
0 |
0 |
T102 |
16176 |
63 |
0 |
0 |
T110 |
35552 |
245 |
0 |
0 |
T114 |
7741 |
76 |
0 |
0 |
T119 |
7535 |
65 |
0 |
0 |
T136 |
12725 |
16 |
0 |
0 |
T137 |
78677 |
116 |
0 |
0 |
T138 |
14506 |
48 |
0 |
0 |
T139 |
19422 |
26 |
0 |
0 |
T140 |
13712 |
47 |
0 |
0 |
T142 |
6615 |
32 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1700 |
0 |
0 |
T102 |
16176 |
126 |
0 |
0 |
T110 |
35552 |
318 |
0 |
0 |
T114 |
7741 |
32 |
0 |
0 |
T119 |
7535 |
69 |
0 |
0 |
T136 |
12725 |
10 |
0 |
0 |
T137 |
78677 |
186 |
0 |
0 |
T138 |
14506 |
50 |
0 |
0 |
T139 |
19422 |
25 |
0 |
0 |
T140 |
13712 |
43 |
0 |
0 |
T142 |
6615 |
4 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1956 |
0 |
0 |
T102 |
16176 |
176 |
0 |
0 |
T110 |
35552 |
373 |
0 |
0 |
T114 |
7741 |
6 |
0 |
0 |
T119 |
7535 |
10 |
0 |
0 |
T137 |
78677 |
127 |
0 |
0 |
T138 |
14506 |
16 |
0 |
0 |
T139 |
19422 |
48 |
0 |
0 |
T140 |
13712 |
38 |
0 |
0 |
T141 |
4787 |
5 |
0 |
0 |
T142 |
6615 |
22 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1787 |
0 |
0 |
T102 |
16176 |
70 |
0 |
0 |
T110 |
35552 |
336 |
0 |
0 |
T114 |
7741 |
60 |
0 |
0 |
T119 |
7535 |
33 |
0 |
0 |
T136 |
12725 |
2 |
0 |
0 |
T137 |
78677 |
163 |
0 |
0 |
T138 |
14506 |
76 |
0 |
0 |
T139 |
19422 |
20 |
0 |
0 |
T140 |
13712 |
38 |
0 |
0 |
T142 |
6615 |
2 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1588 |
0 |
0 |
T102 |
16176 |
113 |
0 |
0 |
T110 |
35552 |
275 |
0 |
0 |
T114 |
7741 |
54 |
0 |
0 |
T119 |
7535 |
65 |
0 |
0 |
T136 |
12725 |
1 |
0 |
0 |
T137 |
78677 |
112 |
0 |
0 |
T138 |
14506 |
47 |
0 |
0 |
T139 |
19422 |
40 |
0 |
0 |
T140 |
13712 |
54 |
0 |
0 |
T142 |
6615 |
19 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1719 |
0 |
0 |
T102 |
16176 |
88 |
0 |
0 |
T110 |
35552 |
291 |
0 |
0 |
T114 |
7741 |
32 |
0 |
0 |
T119 |
7535 |
93 |
0 |
0 |
T136 |
12725 |
34 |
0 |
0 |
T137 |
78677 |
119 |
0 |
0 |
T138 |
14506 |
46 |
0 |
0 |
T139 |
19422 |
69 |
0 |
0 |
T140 |
13712 |
39 |
0 |
0 |
T142 |
6615 |
6 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1906 |
0 |
0 |
T102 |
16176 |
121 |
0 |
0 |
T110 |
35552 |
103 |
0 |
0 |
T114 |
7741 |
56 |
0 |
0 |
T119 |
7535 |
113 |
0 |
0 |
T136 |
12725 |
25 |
0 |
0 |
T137 |
78677 |
119 |
0 |
0 |
T138 |
14506 |
125 |
0 |
0 |
T139 |
19422 |
65 |
0 |
0 |
T140 |
13712 |
98 |
0 |
0 |
T142 |
6615 |
1 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1451 |
0 |
0 |
T102 |
16176 |
26 |
0 |
0 |
T110 |
35552 |
346 |
0 |
0 |
T114 |
7741 |
1 |
0 |
0 |
T119 |
7535 |
58 |
0 |
0 |
T136 |
12725 |
54 |
0 |
0 |
T137 |
78677 |
117 |
0 |
0 |
T138 |
14506 |
37 |
0 |
0 |
T139 |
19422 |
47 |
0 |
0 |
T140 |
13712 |
48 |
0 |
0 |
T141 |
4787 |
2 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1694 |
0 |
0 |
T102 |
16176 |
89 |
0 |
0 |
T110 |
35552 |
297 |
0 |
0 |
T114 |
7741 |
40 |
0 |
0 |
T119 |
7535 |
62 |
0 |
0 |
T136 |
12725 |
22 |
0 |
0 |
T137 |
78677 |
169 |
0 |
0 |
T138 |
14506 |
59 |
0 |
0 |
T139 |
19422 |
19 |
0 |
0 |
T140 |
13712 |
50 |
0 |
0 |
T142 |
6615 |
11 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1824 |
0 |
0 |
T102 |
16176 |
146 |
0 |
0 |
T110 |
35552 |
272 |
0 |
0 |
T114 |
7741 |
15 |
0 |
0 |
T119 |
7535 |
92 |
0 |
0 |
T136 |
12725 |
20 |
0 |
0 |
T137 |
78677 |
152 |
0 |
0 |
T138 |
14506 |
85 |
0 |
0 |
T139 |
19422 |
49 |
0 |
0 |
T140 |
13712 |
32 |
0 |
0 |
T142 |
6615 |
10 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1516 |
0 |
0 |
T102 |
16176 |
26 |
0 |
0 |
T110 |
35552 |
227 |
0 |
0 |
T119 |
7535 |
96 |
0 |
0 |
T136 |
12725 |
3 |
0 |
0 |
T137 |
78677 |
136 |
0 |
0 |
T138 |
14506 |
42 |
0 |
0 |
T139 |
19422 |
38 |
0 |
0 |
T140 |
13712 |
41 |
0 |
0 |
T141 |
4787 |
40 |
0 |
0 |
T142 |
6615 |
14 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
2150 |
0 |
0 |
T102 |
16176 |
13 |
0 |
0 |
T110 |
35552 |
303 |
0 |
0 |
T114 |
7741 |
58 |
0 |
0 |
T119 |
7535 |
58 |
0 |
0 |
T136 |
12725 |
24 |
0 |
0 |
T137 |
78677 |
160 |
0 |
0 |
T138 |
14506 |
34 |
0 |
0 |
T139 |
19422 |
22 |
0 |
0 |
T140 |
13712 |
66 |
0 |
0 |
T142 |
6615 |
7 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1853 |
0 |
0 |
T102 |
16176 |
17 |
0 |
0 |
T110 |
35552 |
307 |
0 |
0 |
T114 |
7741 |
65 |
0 |
0 |
T119 |
7535 |
64 |
0 |
0 |
T136 |
12725 |
49 |
0 |
0 |
T137 |
78677 |
146 |
0 |
0 |
T138 |
14506 |
65 |
0 |
0 |
T139 |
19422 |
25 |
0 |
0 |
T140 |
13712 |
33 |
0 |
0 |
T142 |
6615 |
30 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1696 |
0 |
0 |
T102 |
16176 |
103 |
0 |
0 |
T110 |
35552 |
277 |
0 |
0 |
T114 |
7741 |
7 |
0 |
0 |
T119 |
7535 |
43 |
0 |
0 |
T136 |
12725 |
18 |
0 |
0 |
T137 |
78677 |
159 |
0 |
0 |
T138 |
14506 |
6 |
0 |
0 |
T139 |
19422 |
16 |
0 |
0 |
T140 |
13712 |
54 |
0 |
0 |
T142 |
6615 |
5 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1669 |
0 |
0 |
T102 |
16176 |
60 |
0 |
0 |
T110 |
35552 |
219 |
0 |
0 |
T114 |
7741 |
21 |
0 |
0 |
T119 |
7535 |
38 |
0 |
0 |
T136 |
12725 |
34 |
0 |
0 |
T137 |
78677 |
149 |
0 |
0 |
T138 |
14506 |
51 |
0 |
0 |
T139 |
19422 |
39 |
0 |
0 |
T140 |
13712 |
65 |
0 |
0 |
T142 |
6615 |
5 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1555 |
0 |
0 |
T102 |
16176 |
107 |
0 |
0 |
T110 |
35552 |
325 |
0 |
0 |
T114 |
7741 |
25 |
0 |
0 |
T119 |
7535 |
40 |
0 |
0 |
T136 |
12725 |
10 |
0 |
0 |
T137 |
78677 |
93 |
0 |
0 |
T138 |
14506 |
73 |
0 |
0 |
T139 |
19422 |
35 |
0 |
0 |
T140 |
13712 |
20 |
0 |
0 |
T141 |
4787 |
9 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1843 |
0 |
0 |
T102 |
16176 |
133 |
0 |
0 |
T110 |
35552 |
309 |
0 |
0 |
T114 |
7741 |
46 |
0 |
0 |
T119 |
7535 |
61 |
0 |
0 |
T136 |
12725 |
41 |
0 |
0 |
T137 |
78677 |
160 |
0 |
0 |
T138 |
14506 |
62 |
0 |
0 |
T139 |
19422 |
40 |
0 |
0 |
T140 |
13712 |
21 |
0 |
0 |
T141 |
4787 |
51 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1574 |
0 |
0 |
T102 |
16176 |
116 |
0 |
0 |
T110 |
35552 |
266 |
0 |
0 |
T114 |
7741 |
41 |
0 |
0 |
T119 |
7535 |
4 |
0 |
0 |
T136 |
12725 |
20 |
0 |
0 |
T137 |
78677 |
123 |
0 |
0 |
T138 |
14506 |
66 |
0 |
0 |
T139 |
19422 |
36 |
0 |
0 |
T142 |
6615 |
13 |
0 |
0 |
T143 |
4485 |
4 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1580 |
0 |
0 |
T102 |
16176 |
92 |
0 |
0 |
T110 |
35552 |
136 |
0 |
0 |
T114 |
7741 |
39 |
0 |
0 |
T119 |
7535 |
6 |
0 |
0 |
T136 |
12725 |
16 |
0 |
0 |
T137 |
78677 |
136 |
0 |
0 |
T138 |
14506 |
15 |
0 |
0 |
T139 |
19422 |
28 |
0 |
0 |
T140 |
13712 |
9 |
0 |
0 |
T142 |
6615 |
10 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1898 |
0 |
0 |
T102 |
16176 |
55 |
0 |
0 |
T110 |
35552 |
328 |
0 |
0 |
T114 |
7741 |
30 |
0 |
0 |
T119 |
7535 |
115 |
0 |
0 |
T136 |
12725 |
24 |
0 |
0 |
T137 |
78677 |
106 |
0 |
0 |
T138 |
14506 |
70 |
0 |
0 |
T139 |
19422 |
34 |
0 |
0 |
T140 |
13712 |
15 |
0 |
0 |
T142 |
6615 |
3 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
2063 |
0 |
0 |
T102 |
16176 |
167 |
0 |
0 |
T110 |
35552 |
419 |
0 |
0 |
T114 |
7741 |
23 |
0 |
0 |
T119 |
7535 |
54 |
0 |
0 |
T136 |
12725 |
39 |
0 |
0 |
T137 |
78677 |
151 |
0 |
0 |
T138 |
14506 |
85 |
0 |
0 |
T139 |
19422 |
28 |
0 |
0 |
T140 |
13712 |
34 |
0 |
0 |
T142 |
6615 |
20 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
2027 |
0 |
0 |
T102 |
16176 |
177 |
0 |
0 |
T110 |
35552 |
390 |
0 |
0 |
T114 |
7741 |
4 |
0 |
0 |
T119 |
7535 |
8 |
0 |
0 |
T136 |
12725 |
50 |
0 |
0 |
T137 |
78677 |
168 |
0 |
0 |
T138 |
14506 |
62 |
0 |
0 |
T139 |
19422 |
87 |
0 |
0 |
T140 |
13712 |
46 |
0 |
0 |
T142 |
6615 |
8 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
2029 |
0 |
0 |
T102 |
16176 |
73 |
0 |
0 |
T110 |
35552 |
252 |
0 |
0 |
T114 |
7741 |
54 |
0 |
0 |
T119 |
7535 |
54 |
0 |
0 |
T136 |
12725 |
37 |
0 |
0 |
T137 |
78677 |
159 |
0 |
0 |
T138 |
14506 |
44 |
0 |
0 |
T139 |
19422 |
25 |
0 |
0 |
T140 |
13712 |
25 |
0 |
0 |
T142 |
6615 |
13 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1956 |
0 |
0 |
T102 |
16176 |
141 |
0 |
0 |
T110 |
35552 |
174 |
0 |
0 |
T114 |
7741 |
31 |
0 |
0 |
T119 |
7535 |
79 |
0 |
0 |
T136 |
12725 |
48 |
0 |
0 |
T137 |
78677 |
141 |
0 |
0 |
T138 |
14506 |
63 |
0 |
0 |
T139 |
19422 |
29 |
0 |
0 |
T140 |
13712 |
84 |
0 |
0 |
T142 |
6615 |
5 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
839 |
0 |
0 |
T102 |
16176 |
35 |
0 |
0 |
T110 |
35552 |
36 |
0 |
0 |
T114 |
7741 |
1 |
0 |
0 |
T119 |
7535 |
10 |
0 |
0 |
T136 |
12725 |
41 |
0 |
0 |
T137 |
78677 |
131 |
0 |
0 |
T138 |
14506 |
13 |
0 |
0 |
T139 |
19422 |
28 |
0 |
0 |
T140 |
13712 |
65 |
0 |
0 |
T141 |
4787 |
6 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
905 |
0 |
0 |
T102 |
16176 |
19 |
0 |
0 |
T110 |
35552 |
55 |
0 |
0 |
T114 |
7741 |
7 |
0 |
0 |
T119 |
7535 |
15 |
0 |
0 |
T136 |
12725 |
22 |
0 |
0 |
T137 |
78677 |
115 |
0 |
0 |
T138 |
14506 |
20 |
0 |
0 |
T139 |
19422 |
42 |
0 |
0 |
T140 |
13712 |
78 |
0 |
0 |
T142 |
6615 |
16 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
774 |
0 |
0 |
T102 |
16176 |
20 |
0 |
0 |
T110 |
35552 |
42 |
0 |
0 |
T114 |
7741 |
6 |
0 |
0 |
T119 |
7535 |
21 |
0 |
0 |
T136 |
12725 |
15 |
0 |
0 |
T137 |
78677 |
116 |
0 |
0 |
T138 |
14506 |
25 |
0 |
0 |
T139 |
19422 |
15 |
0 |
0 |
T140 |
13712 |
99 |
0 |
0 |
T142 |
6615 |
2 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
751 |
0 |
0 |
T102 |
16176 |
26 |
0 |
0 |
T110 |
35552 |
55 |
0 |
0 |
T114 |
7741 |
10 |
0 |
0 |
T119 |
7535 |
9 |
0 |
0 |
T136 |
12725 |
5 |
0 |
0 |
T137 |
78677 |
126 |
0 |
0 |
T138 |
14506 |
22 |
0 |
0 |
T139 |
19422 |
8 |
0 |
0 |
T140 |
13712 |
42 |
0 |
0 |
T142 |
6615 |
21 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1043 |
0 |
0 |
T102 |
16176 |
49 |
0 |
0 |
T110 |
35552 |
107 |
0 |
0 |
T114 |
7741 |
14 |
0 |
0 |
T119 |
7535 |
40 |
0 |
0 |
T136 |
12725 |
14 |
0 |
0 |
T137 |
78677 |
130 |
0 |
0 |
T138 |
14506 |
16 |
0 |
0 |
T139 |
19422 |
15 |
0 |
0 |
T140 |
13712 |
41 |
0 |
0 |
T142 |
6615 |
9 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1815 |
0 |
0 |
T31 |
0 |
19 |
0 |
0 |
T128 |
0 |
14 |
0 |
0 |
T134 |
158852 |
0 |
0 |
0 |
T135 |
30295 |
0 |
0 |
0 |
T144 |
393091 |
62 |
0 |
0 |
T145 |
0 |
5 |
0 |
0 |
T146 |
0 |
15 |
0 |
0 |
T147 |
0 |
21 |
0 |
0 |
T148 |
0 |
40 |
0 |
0 |
T149 |
0 |
52 |
0 |
0 |
T150 |
0 |
20 |
0 |
0 |
T151 |
0 |
30 |
0 |
0 |
T152 |
25964 |
0 |
0 |
0 |
T153 |
88610 |
0 |
0 |
0 |
T154 |
621625 |
0 |
0 |
0 |
T155 |
46942 |
0 |
0 |
0 |
T156 |
237766 |
0 |
0 |
0 |
T157 |
226334 |
0 |
0 |
0 |
T158 |
157797 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
792 |
0 |
0 |
T102 |
16176 |
12 |
0 |
0 |
T110 |
35552 |
61 |
0 |
0 |
T119 |
7535 |
4 |
0 |
0 |
T136 |
12725 |
24 |
0 |
0 |
T137 |
78677 |
128 |
0 |
0 |
T138 |
14506 |
9 |
0 |
0 |
T139 |
19422 |
46 |
0 |
0 |
T140 |
13712 |
65 |
0 |
0 |
T141 |
4787 |
13 |
0 |
0 |
T142 |
6615 |
11 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
789 |
0 |
0 |
T102 |
16176 |
26 |
0 |
0 |
T110 |
35552 |
59 |
0 |
0 |
T114 |
7741 |
8 |
0 |
0 |
T119 |
7535 |
8 |
0 |
0 |
T136 |
12725 |
4 |
0 |
0 |
T137 |
78677 |
114 |
0 |
0 |
T138 |
14506 |
27 |
0 |
0 |
T139 |
19422 |
35 |
0 |
0 |
T140 |
13712 |
31 |
0 |
0 |
T142 |
6615 |
18 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
708 |
0 |
0 |
T102 |
16176 |
28 |
0 |
0 |
T110 |
35552 |
39 |
0 |
0 |
T114 |
7741 |
3 |
0 |
0 |
T119 |
7535 |
12 |
0 |
0 |
T136 |
12725 |
10 |
0 |
0 |
T137 |
78677 |
159 |
0 |
0 |
T138 |
14506 |
10 |
0 |
0 |
T139 |
19422 |
18 |
0 |
0 |
T140 |
13712 |
43 |
0 |
0 |
T142 |
6615 |
8 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
681 |
0 |
0 |
T102 |
16176 |
21 |
0 |
0 |
T110 |
35552 |
42 |
0 |
0 |
T114 |
7741 |
6 |
0 |
0 |
T119 |
7535 |
7 |
0 |
0 |
T136 |
12725 |
24 |
0 |
0 |
T137 |
78677 |
151 |
0 |
0 |
T138 |
14506 |
2 |
0 |
0 |
T139 |
19422 |
57 |
0 |
0 |
T140 |
13712 |
26 |
0 |
0 |
T142 |
6615 |
2 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
670 |
0 |
0 |
T102 |
16176 |
16 |
0 |
0 |
T110 |
35552 |
36 |
0 |
0 |
T114 |
7741 |
10 |
0 |
0 |
T119 |
7535 |
3 |
0 |
0 |
T136 |
12725 |
38 |
0 |
0 |
T137 |
78677 |
115 |
0 |
0 |
T138 |
14506 |
11 |
0 |
0 |
T139 |
19422 |
23 |
0 |
0 |
T140 |
13712 |
8 |
0 |
0 |
T142 |
6615 |
9 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
756 |
0 |
0 |
T102 |
16176 |
21 |
0 |
0 |
T110 |
35552 |
51 |
0 |
0 |
T119 |
7535 |
14 |
0 |
0 |
T136 |
12725 |
6 |
0 |
0 |
T137 |
78677 |
137 |
0 |
0 |
T138 |
14506 |
2 |
0 |
0 |
T139 |
19422 |
31 |
0 |
0 |
T140 |
13712 |
40 |
0 |
0 |
T141 |
4787 |
9 |
0 |
0 |
T142 |
6615 |
21 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
992 |
0 |
0 |
T102 |
16176 |
23 |
0 |
0 |
T110 |
35552 |
114 |
0 |
0 |
T114 |
7741 |
21 |
0 |
0 |
T119 |
7535 |
29 |
0 |
0 |
T136 |
12725 |
7 |
0 |
0 |
T137 |
78677 |
145 |
0 |
0 |
T138 |
14506 |
7 |
0 |
0 |
T139 |
19422 |
37 |
0 |
0 |
T140 |
13712 |
33 |
0 |
0 |
T142 |
6615 |
16 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
807 |
0 |
0 |
T102 |
16176 |
12 |
0 |
0 |
T110 |
35552 |
43 |
0 |
0 |
T114 |
7741 |
2 |
0 |
0 |
T119 |
7535 |
10 |
0 |
0 |
T136 |
12725 |
41 |
0 |
0 |
T137 |
78677 |
156 |
0 |
0 |
T138 |
14506 |
22 |
0 |
0 |
T139 |
19422 |
14 |
0 |
0 |
T140 |
13712 |
46 |
0 |
0 |
T142 |
6615 |
14 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
1214 |
0 |
0 |
T102 |
16176 |
27 |
0 |
0 |
T110 |
35552 |
159 |
0 |
0 |
T114 |
7741 |
3 |
0 |
0 |
T119 |
7535 |
20 |
0 |
0 |
T136 |
12725 |
32 |
0 |
0 |
T137 |
78677 |
150 |
0 |
0 |
T138 |
14506 |
36 |
0 |
0 |
T139 |
19422 |
50 |
0 |
0 |
T140 |
13712 |
68 |
0 |
0 |
T142 |
6615 |
5 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
819 |
0 |
0 |
T102 |
16176 |
46 |
0 |
0 |
T110 |
35552 |
60 |
0 |
0 |
T119 |
7535 |
20 |
0 |
0 |
T136 |
12725 |
23 |
0 |
0 |
T137 |
78677 |
147 |
0 |
0 |
T138 |
14506 |
20 |
0 |
0 |
T139 |
19422 |
32 |
0 |
0 |
T140 |
13712 |
36 |
0 |
0 |
T142 |
6615 |
10 |
0 |
0 |
T159 |
4906 |
1 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
618 |
0 |
0 |
T102 |
16176 |
15 |
0 |
0 |
T110 |
35552 |
49 |
0 |
0 |
T114 |
7741 |
5 |
0 |
0 |
T136 |
12725 |
13 |
0 |
0 |
T137 |
78677 |
74 |
0 |
0 |
T138 |
14506 |
15 |
0 |
0 |
T139 |
19422 |
30 |
0 |
0 |
T140 |
13712 |
37 |
0 |
0 |
T141 |
4787 |
4 |
0 |
0 |
T142 |
6615 |
2 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
787 |
0 |
0 |
T102 |
16176 |
33 |
0 |
0 |
T110 |
35552 |
66 |
0 |
0 |
T114 |
7741 |
3 |
0 |
0 |
T119 |
7535 |
8 |
0 |
0 |
T136 |
12725 |
23 |
0 |
0 |
T137 |
78677 |
147 |
0 |
0 |
T138 |
14506 |
22 |
0 |
0 |
T139 |
19422 |
70 |
0 |
0 |
T140 |
13712 |
32 |
0 |
0 |
T142 |
6615 |
20 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
726 |
0 |
0 |
T102 |
16176 |
28 |
0 |
0 |
T110 |
35552 |
30 |
0 |
0 |
T119 |
7535 |
2 |
0 |
0 |
T136 |
12725 |
17 |
0 |
0 |
T137 |
78677 |
126 |
0 |
0 |
T138 |
14506 |
7 |
0 |
0 |
T139 |
19422 |
33 |
0 |
0 |
T140 |
13712 |
60 |
0 |
0 |
T141 |
4787 |
2 |
0 |
0 |
T160 |
7320 |
44 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
734 |
0 |
0 |
T91 |
7753 |
1 |
0 |
0 |
T102 |
16176 |
16 |
0 |
0 |
T110 |
35552 |
42 |
0 |
0 |
T114 |
7741 |
9 |
0 |
0 |
T119 |
7535 |
6 |
0 |
0 |
T136 |
12725 |
25 |
0 |
0 |
T137 |
78677 |
129 |
0 |
0 |
T138 |
14506 |
5 |
0 |
0 |
T139 |
19422 |
31 |
0 |
0 |
T142 |
6615 |
14 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
755 |
0 |
0 |
T102 |
16176 |
14 |
0 |
0 |
T110 |
35552 |
40 |
0 |
0 |
T114 |
7741 |
3 |
0 |
0 |
T119 |
7535 |
8 |
0 |
0 |
T136 |
12725 |
26 |
0 |
0 |
T137 |
78677 |
163 |
0 |
0 |
T138 |
14506 |
12 |
0 |
0 |
T139 |
19422 |
61 |
0 |
0 |
T140 |
13712 |
32 |
0 |
0 |
T142 |
6615 |
15 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456106690 |
710 |
0 |
0 |
T102 |
16176 |
31 |
0 |
0 |
T110 |
35552 |
66 |
0 |
0 |
T114 |
7741 |
7 |
0 |
0 |
T119 |
7535 |
4 |
0 |
0 |
T136 |
12725 |
26 |
0 |
0 |
T137 |
78677 |
125 |
0 |
0 |
T138 |
14506 |
20 |
0 |
0 |
T139 |
19422 |
25 |
0 |
0 |
T140 |
13712 |
23 |
0 |
0 |
T142 |
6615 |
8 |
0 |
0 |