Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3486531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4277356

1

T1

3880

T2

1473

T3

6953

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4231832	1			T1	5933		T2	150		T3	2544
values[0x0]	1766499	1			T1	444		T2	703		T3	3245
values[0x1]	1765556	1			T1	438		T2	696		T3	3217

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2480195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5283692

1

T1

4441

T2

1488

T3

7540

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32743	1			T1	23		T3	30		T5	52
valid_sources[0x01]	27843	1			T1	27		T3	37		T4	2
valid_sources[0x02]	31197	1			T1	22		T3	32		T5	60
valid_sources[0x03]	34428	1			T1	27		T3	34		T5	55
valid_sources[0x04]	31807	1			T1	17		T3	44		T4	1
valid_sources[0x05]	33683	1			T1	17		T3	35		T5	50
valid_sources[0x06]	32130	1			T1	46		T3	32		T5	59
valid_sources[0x07]	32544	1			T1	22		T2	3		T3	44
valid_sources[0x08]	27985	1			T1	34		T3	35		T5	46
valid_sources[0x09]	27555	1			T1	20		T2	37		T3	49
valid_sources[0x0a]	26908	1			T1	35		T3	46		T5	49
valid_sources[0x0b]	28601	1			T1	12		T3	47		T5	52
valid_sources[0x0c]	27340	1			T1	46		T3	37		T4	2
valid_sources[0x0d]	31871	1			T1	22		T2	27		T3	39
valid_sources[0x0e]	26177	1			T1	28		T3	34		T5	61
valid_sources[0x0f]	30697	1			T1	44		T3	32		T4	3
valid_sources[0x10]	33578	1			T1	32		T2	22		T3	37
valid_sources[0x11]	29200	1			T1	26		T3	36		T5	43
valid_sources[0x12]	32104	1			T1	39		T3	31		T5	53
valid_sources[0x13]	37795	1			T1	26		T3	35		T5	26
valid_sources[0x14]	36211	1			T1	17		T3	29		T4	2
valid_sources[0x15]	27770	1			T1	30		T3	34		T5	52
valid_sources[0x16]	29464	1			T1	32		T3	32		T4	1
valid_sources[0x17]	29764	1			T1	30		T3	33		T5	49
valid_sources[0x18]	34539	1			T1	34		T3	45		T4	1
valid_sources[0x19]	29004	1			T1	22		T3	39		T5	45
valid_sources[0x1a]	28369	1			T1	25		T3	31		T5	42
valid_sources[0x1b]	27692	1			T1	40		T3	26		T5	50
valid_sources[0x1c]	27505	1			T1	20		T3	37		T5	51
valid_sources[0x1d]	26540	1			T1	41		T3	41		T4	3
valid_sources[0x1e]	27738	1			T1	35		T3	47		T4	3
valid_sources[0x1f]	27271	1			T1	18		T2	2		T3	24
valid_sources[0x20]	29533	1			T1	31		T3	42		T5	48
valid_sources[0x21]	27825	1			T1	22		T3	29		T5	35
valid_sources[0x22]	25638	1			T1	34		T3	26		T5	48
valid_sources[0x23]	31249	1			T1	45		T2	6		T3	36
valid_sources[0x24]	27380	1			T1	30		T3	29		T4	1
valid_sources[0x25]	29047	1			T1	28		T3	27		T5	58
valid_sources[0x26]	27655	1			T1	29		T3	41		T4	3
valid_sources[0x27]	28097	1			T1	45		T3	32		T4	1
valid_sources[0x28]	32123	1			T1	30		T3	32		T5	56
valid_sources[0x29]	26309	1			T1	23		T3	35		T4	1
valid_sources[0x2a]	28557	1			T1	15		T3	50		T5	49
valid_sources[0x2b]	26026	1			T1	45		T3	35		T4	1
valid_sources[0x2c]	92276	1			T1	14		T3	44		T5	54
valid_sources[0x2d]	26717	1			T1	16		T3	36		T5	56
valid_sources[0x2e]	29274	1			T1	31		T3	38		T5	65
valid_sources[0x2f]	29921	1			T1	23		T3	36		T5	60
valid_sources[0x30]	28226	1			T1	27		T3	30		T5	43
valid_sources[0x31]	45225	1			T1	23		T2	49		T3	50
valid_sources[0x32]	28457	1			T1	37		T3	31		T4	1
valid_sources[0x33]	27708	1			T1	30		T3	39		T5	51
valid_sources[0x34]	26595	1			T1	39		T3	30		T5	48
valid_sources[0x35]	29709	1			T1	22		T3	22		T5	46
valid_sources[0x36]	30893	1			T1	35		T2	1		T3	45
valid_sources[0x37]	31764	1			T1	23		T3	31		T5	39
valid_sources[0x38]	27500	1			T1	31		T2	1		T3	44
valid_sources[0x39]	27251	1			T1	42		T3	23		T5	46
valid_sources[0x3a]	26767	1			T1	44		T3	33		T5	42
valid_sources[0x3b]	25701	1			T1	21		T2	47		T3	25
valid_sources[0x3c]	29148	1			T1	17		T3	43		T5	51
valid_sources[0x3d]	28650	1			T1	15		T3	34		T5	45
valid_sources[0x3e]	26825	1			T1	20		T2	75		T3	34
valid_sources[0x3f]	30073	1			T1	2		T3	35		T4	3
valid_sources[0x40]	35954	1			T1	45		T2	17		T3	39
valid_sources[0x41]	31959	1			T1	24		T2	32		T3	37
valid_sources[0x42]	30850	1			T1	20		T3	41		T4	3
valid_sources[0x43]	28819	1			T1	25		T3	34		T5	54
valid_sources[0x44]	27247	1			T1	29		T3	39		T5	42
valid_sources[0x45]	30793	1			T1	29		T3	24		T5	53
valid_sources[0x46]	29259	1			T1	27		T3	31		T5	55
valid_sources[0x47]	27883	1			T1	13		T3	22		T4	1
valid_sources[0x48]	28370	1			T1	31		T3	43		T4	1
valid_sources[0x49]	28876	1			T1	36		T2	9		T3	33
valid_sources[0x4a]	29419	1			T1	33		T3	36		T5	48
valid_sources[0x4b]	27968	1			T1	52		T3	33		T4	1
valid_sources[0x4c]	32789	1			T1	23		T2	31		T3	38
valid_sources[0x4d]	30361	1			T1	36		T3	35		T5	60
valid_sources[0x4e]	35105	1			T1	38		T3	29		T5	45
valid_sources[0x4f]	31074	1			T1	26		T3	35		T5	42
valid_sources[0x50]	27119	1			T1	17		T2	30		T3	38
valid_sources[0x51]	29821	1			T1	26		T3	47		T4	5
valid_sources[0x52]	44596	1			T1	10		T3	35		T4	2
valid_sources[0x53]	27687	1			T1	9		T3	41		T5	43
valid_sources[0x54]	32981	1			T1	22		T3	34		T5	56
valid_sources[0x55]	30373	1			T1	21		T3	28		T5	62
valid_sources[0x56]	27833	1			T1	20		T2	71		T3	38
valid_sources[0x57]	28849	1			T1	22		T3	32		T5	47
valid_sources[0x58]	26850	1			T1	30		T3	46		T5	39
valid_sources[0x59]	30409	1			T1	30		T2	69		T3	35
valid_sources[0x5a]	32475	1			T1	30		T3	30		T5	47
valid_sources[0x5b]	26550	1			T1	13		T3	28		T5	55
valid_sources[0x5c]	27465	1			T1	46		T2	23		T3	34
valid_sources[0x5d]	31859	1			T1	27		T3	42		T5	59
valid_sources[0x5e]	28465	1			T1	27		T3	39		T4	1
valid_sources[0x5f]	31191	1			T1	45		T3	40		T5	60
valid_sources[0x60]	28324	1			T1	25		T3	26		T5	32
valid_sources[0x61]	28514	1			T1	23		T2	19		T3	42
valid_sources[0x62]	34501	1			T1	36		T3	31		T4	1
valid_sources[0x63]	34590	1			T1	28		T2	10		T3	37
valid_sources[0x64]	28823	1			T1	30		T3	43		T5	45
valid_sources[0x65]	29766	1			T1	15		T3	45		T5	47
valid_sources[0x66]	28782	1			T1	15		T2	8		T3	46
valid_sources[0x67]	32548	1			T1	47		T2	7		T3	31
valid_sources[0x68]	32184	1			T1	12		T3	40		T5	42
valid_sources[0x69]	30726	1			T1	26		T3	38		T5	48
valid_sources[0x6a]	29920	1			T1	30		T3	31		T4	1
valid_sources[0x6b]	26774	1			T1	23		T3	41		T5	48
valid_sources[0x6c]	30266	1			T1	26		T3	24		T5	73
valid_sources[0x6d]	29994	1			T1	22		T3	26		T5	55
valid_sources[0x6e]	28796	1			T1	26		T3	42		T5	52
valid_sources[0x6f]	29810	1			T1	12		T3	40		T5	52
valid_sources[0x70]	26229	1			T1	21		T3	41		T5	44
valid_sources[0x71]	33284	1			T1	31		T3	32		T5	46
valid_sources[0x72]	29545	1			T1	44		T3	23		T5	37
valid_sources[0x73]	28096	1			T1	29		T3	45		T5	46
valid_sources[0x74]	26639	1			T1	24		T3	40		T4	1
valid_sources[0x75]	27925	1			T1	17		T3	48		T5	54
valid_sources[0x76]	32910	1			T1	36		T3	36		T5	49
valid_sources[0x77]	29009	1			T1	9		T3	22		T4	1
valid_sources[0x78]	28401	1			T1	18		T2	13		T3	37
valid_sources[0x79]	27572	1			T1	15		T3	34		T5	40
valid_sources[0x7a]	32531	1			T1	30		T2	137		T3	22
valid_sources[0x7b]	36642	1			T1	37		T3	33		T5	42
valid_sources[0x7c]	33737	1			T1	19		T3	34		T5	55
valid_sources[0x7d]	34744	1			T1	13		T2	18		T3	34
valid_sources[0x7e]	30136	1			T1	29		T3	23		T4	1
valid_sources[0x7f]	27706	1			T1	15		T3	28		T5	41
valid_sources[0x80]	28117	1			T1	13		T3	22		T5	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1066954

1

T1

3004

T2

82

T3

820

values[0x0]

all_enables

biggest_size

1617618

1

T1

442

T2

701

T3

3085

values[0x1]

all_enables

biggest_size

1592784

1

T1

434

T2

690

T3

3048