Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3504054

1

T1

2935

T2

76

T3

2053

full_word

4278384

1

T1

3880

T2

1473

T3

6953

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7782088	1			T1	6815		T2	1549		T3	9006
auto[TlIntgErrCmd]	103	1			T61	2		T63	5		T100	2
auto[TlIntgErrData]	118	1			T61	7		T63	9		T100	5
auto[TlIntgErrBoth]	129	1			T61	1		T63	6		T100	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4234957

1

T1

5933

T2

150

T3

2544

auto[1]

3547481

1

T1

882

T2

1399

T3

6462

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3167601	1			T1	2929		T2	68		T3	1724
auto[TlIntgErrNone]	partial	auto[1]	336129	1			T1	6		T2	8		T3	329
auto[TlIntgErrNone]	full_word	auto[0]	1067194	1			T1	3004		T2	82		T3	820
auto[TlIntgErrNone]	full_word	auto[1]	3211164	1			T1	876		T2	1391		T3	6133
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T63	1		T100	2		T118	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T61	2		T63	3		T118	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T118	1		T163	1		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T63	1		T165	1		T162	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T61	4		T63	4		T100	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T61	3		T63	3		T100	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T63	2		T160	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T100	1		T161	1		T162	2
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T63	1		T118	6		T115	4
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T61	1		T63	4		T100	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T63	1		T118	1		T159	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T166	1		T163	1