Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	626234308	3333480	0	0
gen_wmask[1].MaskCheckPortA_A	626234308	3333480	0	0
gen_wmask[2].MaskCheckPortA_A	626234308	3333480	0	0
gen_wmask[3].MaskCheckPortA_A	626234308	3333480	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626234308	3333480	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	769422	14898	0	0
T4	2770	7	0	0
T5	949137	10135	0	0
T6	94976	832	0	0
T7	55117	1088	0	0
T8	128461	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	8224	832	0	0
T14	393915	10820	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626234308	3333480	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	769422	14898	0	0
T4	2770	7	0	0
T5	949137	10135	0	0
T6	94976	832	0	0
T7	55117	1088	0	0
T8	128461	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	8224	832	0	0
T14	393915	10820	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626234308	3333480	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	769422	14898	0	0
T4	2770	7	0	0
T5	949137	10135	0	0
T6	94976	832	0	0
T7	55117	1088	0	0
T8	128461	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	8224	832	0	0
T14	393915	10820	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626234308	3333480	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	769422	14898	0	0
T4	2770	7	0	0
T5	949137	10135	0	0
T6	94976	832	0	0
T7	55117	1088	0	0
T8	128461	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	8224	832	0	0
T14	393915	10820	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	477693495	2133624	0	0
gen_wmask[1].MaskCheckPortA_A	477693495	2133624	0	0
gen_wmask[2].MaskCheckPortA_A	477693495	2133624	0	0
gen_wmask[3].MaskCheckPortA_A	477693495	2133624	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2133624	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5209	0	0
T4	2554	1	0	0
T5	358126	6656	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	7662	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2133624	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5209	0	0
T4	2554	1	0	0
T5	358126	6656	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	7662	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2133624	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5209	0	0
T4	2554	1	0	0
T5	358126	6656	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	7662	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2133624	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5209	0	0
T4	2554	1	0	0
T5	358126	6656	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	7662	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	148540813	1199856	0	0
gen_wmask[1].MaskCheckPortA_A	148540813	1199856	0	0
gen_wmask[2].MaskCheckPortA_A	148540813	1199856	0	0
gen_wmask[3].MaskCheckPortA_A	148540813	1199856	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	1199856	0	0
T3	469913	9689	0	0
T4	216	6	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3158	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	1199856	0	0
T3	469913	9689	0	0
T4	216	6	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3158	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	1199856	0	0
T3	469913	9689	0	0
T4	216	6	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3158	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	1199856	0	0
T3	469913	9689	0	0
T4	216	6	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3158	0	0
T15	191911	0	0	0
T16	0	11530	0	0
T17	0	5237	0	0
T26	151	0	0	0
T31	0	6313	0	0
T33	0	4036	0	0
T38	0	3835	0	0
T39	0	2181	0	0