Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	2991853	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	2991853	0	0
T1	144372	1663	0	0
T2	12211	1854	0	0
T3	299509	5823	0	0
T4	2554	0	0	0
T5	358126	11665	0	0
T6	83307	1663	0	0
T7	43632	1343	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	10812	0	0
T24	0	1665	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	3195695	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	3195695	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	4992	0	0
T4	2554	0	0	0
T5	358126	12606	0	0
T6	83307	832	0	0
T7	43632	2904	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	2573	0	0
T14	0	7488	0	0
T24	0	834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	182462	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	182462	0	0
T3	299509	529	0	0
T4	2554	2	0	0
T5	358126	305	0	0
T6	83307	0	0	0
T7	43632	0	0	0
T8	103525	0	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T11	1558	0	0	0
T12	5316	0	0	0
T14	0	487	0	0
T16	0	2315	0	0
T17	0	449	0	0
T31	0	603	0	0
T33	0	834	0	0
T38	0	501	0	0
T39	0	225	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	410389	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	410389	0	0
T3	299509	529	0	0
T4	2554	5	0	0
T5	358126	1329	0	0
T6	83307	0	0	0
T7	43632	0	0	0
T8	103525	0	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T11	1558	0	0	0
T12	5316	0	0	0
T14	0	487	0	0
T16	0	2315	0	0
T17	0	449	0	0
T31	0	2706	0	0
T33	0	834	0	0
T38	0	2227	0	0
T39	0	1053	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	6020320	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	6020320	0	0
T1	144372	5988	0	0
T2	12211	205	0	0
T3	299509	3512	0	0
T4	2554	107	0	0
T5	358126	5667	0	0
T6	83307	61	0	0
T7	43632	1178	0	0
T8	103525	202	0	0
T9	1419	18	0	0
T10	1064	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479806074	12444541	0	0
DepthKnown_A	479806074	479676979	0	0
RvalidKnown_A	479806074	479676979	0	0
WreadyKnown_A	479806074	479676979	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	12444541	0	0
T1	144372	17917	0	0
T2	12211	205	0	0
T3	299509	3485	0	0
T4	2554	486	0	0
T5	358126	24505	0	0
T6	83307	100	0	0
T7	43632	3537	0	0
T8	103525	202	0	0
T9	1419	18	0	0
T10	1064	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479806074	479676979	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0