Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T14
1	0	Covered	T3,T4,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Unreachable
1	1	Covered	T3,T4,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	774775121	624808856	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	774775121	3712673	0	0
GntImpliesValid_A	774775121	3712673	0	0
GrantKnown_A	774775121	624808856	0	0
IdxKnown_A	774775121	624808856	0	0
IndexIsCorrect_A	774775121	3712673	0	0
LockArbDecision_A	774775121	0	0	0
NoReadyValidNoGrant_A	774775121	0	0	0
ReadyAndValidImplyGrant_A	774775121	3712673	0	0
ReqAndReadyImplyGrant_A	774775121	3712673	0	0
ReqImpliesValid_A	774775121	3712673	0	0
ReqStaysHighUntilGranted0_M	774775121	0	0	0
RoundRobin_A	774775121	7	0	954
ValidKnown_A	774775121	624808856	0	0
gen_data_port_assertion.DataFlow_A	774775121	3712673	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	624808856	0	0
T1	161996	161911	0	0
T2	29326	29229	0	0
T3	1239335	765920	0	0
T4	2986	2713	0	0
T5	1540148	946499	0	0
T6	106645	94584	0	0
T7	66602	55031	0	0
T8	153397	128363	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0
T13	16448	8224	0	0
T14	787830	392065	0	0
T15	191911	190992	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	624808856	0	0
T1	161996	161911	0	0
T2	29326	29229	0	0
T3	1239335	765920	0	0
T4	2986	2713	0	0
T5	1540148	946499	0	0
T6	106645	94584	0	0
T7	66602	55031	0	0
T8	153397	128363	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0
T13	16448	8224	0	0
T14	787830	392065	0	0
T15	191911	190992	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	624808856	0	0
T1	161996	161911	0	0
T2	29326	29229	0	0
T3	1239335	765920	0	0
T4	2986	2713	0	0
T5	1540148	946499	0	0
T6	106645	94584	0	0
T7	66602	55031	0	0
T8	153397	128363	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0
T13	16448	8224	0	0
T14	787830	392065	0	0
T15	191911	190992	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	7	0	954
T18	278743	0	0	1
T34	646673	1	0	1
T48	299837	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	45178	0	0	1
T55	12055	0	0	1
T56	815	0	0	1
T57	126260	0	0	1
T58	98819	0	0	1
T59	21210	0	0	1
T60	1327	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	624808856	0	0
T1	161996	161911	0	0
T2	29326	29229	0	0
T3	1239335	765920	0	0
T4	2986	2713	0	0
T5	1540148	946499	0	0
T6	106645	94584	0	0
T7	66602	55031	0	0
T8	153397	128363	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0
T13	16448	8224	0	0
T14	787830	392065	0	0
T15	191911	190992	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774775121	3712673	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	1239335	15676	0	0
T4	2986	11	0	0
T5	1540148	10460	0	0
T6	106645	832	0	0
T7	66602	1088	0	0
T8	153397	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	16448	832	0	0
T14	787830	11520	0	0
T15	383822	0	0	0
T16	0	14065	0	0
T17	0	5678	0	0
T18	0	4584	0	0
T26	302	0	0	0
T31	0	6760	0	0
T33	0	5177	0	0
T34	0	4902	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0
T48	0	308	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T14
1	0	Covered	T3,T4,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Unreachable
1	1	Covered	T3,T4,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T14
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148540813	26475898	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	148540813	617722	0	0
GntImpliesValid_A	148540813	617722	0	0
GrantKnown_A	148540813	26475898	0	0
IdxKnown_A	148540813	26475898	0	0
IndexIsCorrect_A	148540813	617722	0	0
LockArbDecision_A	148540813	0	0	0
NoReadyValidNoGrant_A	148540813	0	0	0
ReadyAndValidImplyGrant_A	148540813	617722	0	0
ReqAndReadyImplyGrant_A	148540813	617722	0	0
ReqImpliesValid_A	148540813	617722	0	0
ReqStaysHighUntilGranted0_M	148540813	0	0	0
RoundRobin_A	148540813	0	0	0
ValidKnown_A	148540813	26475898	0	0
gen_data_port_assertion.DataFlow_A	148540813	617722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	26475898	0	0
T3	469913	45520	0	0
T4	216	216	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	12024	0	0
T15	191911	0	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	26475898	0	0
T3	469913	45520	0	0
T4	216	216	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	12024	0	0
T15	191911	0	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	26475898	0	0
T3	469913	45520	0	0
T4	216	216	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	12024	0	0
T15	191911	0	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	26475898	0	0
T3	469913	45520	0	0
T4	216	216	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	12024	0	0
T15	191911	0	0	0
T16	0	177056	0	0
T17	0	30048	0	0
T26	151	0	0	0
T27	0	144	0	0
T30	0	38240	0	0
T31	0	53640	0	0
T33	0	78912	0	0
T34	0	213736	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	617722	0	0
T3	469913	898	0	0
T4	216	8	0	0
T5	591011	0	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	338	0	0
T15	191911	0	0	0
T16	0	8479	0	0
T17	0	1253	0	0
T18	0	4584	0	0
T26	151	0	0	0
T31	0	1003	0	0
T33	0	3361	0	0
T34	0	4902	0	0
T48	0	308	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T14
1	0	Covered	T3,T5,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148540813	120726900	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	148540813	784725	0	0
GntImpliesValid_A	148540813	784725	0	0
GrantKnown_A	148540813	120726900	0	0
IdxKnown_A	148540813	120726900	0	0
IndexIsCorrect_A	148540813	784725	0	0
LockArbDecision_A	148540813	0	0	0
NoReadyValidNoGrant_A	148540813	0	0	0
ReadyAndValidImplyGrant_A	148540813	784725	0	0
ReqAndReadyImplyGrant_A	148540813	784725	0	0
ReqImpliesValid_A	148540813	784725	0	0
ReqStaysHighUntilGranted0_M	148540813	0	0	0
RoundRobin_A	148540813	0	0	0
ValidKnown_A	148540813	120726900	0	0
gen_data_port_assertion.DataFlow_A	148540813	784725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	120726900	0	0
T1	17624	17624	0	0
T2	17115	17115	0	0
T3	469913	420978	0	0
T4	216	0	0	0
T5	591011	588382	0	0
T6	11669	11368	0	0
T7	11485	11485	0	0
T8	24936	24936	0	0
T13	8224	8224	0	0
T14	393915	380041	0	0
T15	0	190992	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	120726900	0	0
T1	17624	17624	0	0
T2	17115	17115	0	0
T3	469913	420978	0	0
T4	216	0	0	0
T5	591011	588382	0	0
T6	11669	11368	0	0
T7	11485	11485	0	0
T8	24936	24936	0	0
T13	8224	8224	0	0
T14	393915	380041	0	0
T15	0	190992	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	120726900	0	0
T1	17624	17624	0	0
T2	17115	17115	0	0
T3	469913	420978	0	0
T4	216	0	0	0
T5	591011	588382	0	0
T6	11669	11368	0	0
T7	11485	11485	0	0
T8	24936	24936	0	0
T13	8224	8224	0	0
T14	393915	380041	0	0
T15	0	190992	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	120726900	0	0
T1	17624	17624	0	0
T2	17115	17115	0	0
T3	469913	420978	0	0
T4	216	0	0	0
T5	591011	588382	0	0
T6	11669	11368	0	0
T7	11485	11485	0	0
T8	24936	24936	0	0
T13	8224	8224	0	0
T14	393915	380041	0	0
T15	0	190992	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148540813	784725	0	0
T3	469913	9023	0	0
T4	216	0	0	0
T5	591011	3479	0	0
T6	11669	0	0	0
T7	11485	0	0	0
T8	24936	0	0	0
T13	8224	0	0	0
T14	393915	3008	0	0
T15	191911	0	0	0
T16	0	5586	0	0
T17	0	4425	0	0
T26	151	0	0	0
T31	0	5757	0	0
T33	0	1816	0	0
T38	0	3835	0	0
T39	0	2181	0	0
T42	0	1019	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	477693495	477606058	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	477693495	2310226	0	0
GntImpliesValid_A	477693495	2310226	0	0
GrantKnown_A	477693495	477606058	0	0
IdxKnown_A	477693495	477606058	0	0
IndexIsCorrect_A	477693495	2310226	0	0
LockArbDecision_A	477693495	0	0	0
NoReadyValidNoGrant_A	477693495	0	0	0
ReadyAndValidImplyGrant_A	477693495	2310226	0	0
ReqAndReadyImplyGrant_A	477693495	2310226	0	0
ReqImpliesValid_A	477693495	2310226	0	0
ReqStaysHighUntilGranted0_M	477693495	0	0	0
RoundRobin_A	477693495	7	0	954
ValidKnown_A	477693495	477606058	0	0
gen_data_port_assertion.DataFlow_A	477693495	2310226	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	477606058	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	477606058	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	477606058	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	7	0	954
T18	278743	0	0	1
T34	646673	1	0	1
T48	299837	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	45178	0	0	1
T55	12055	0	0	1
T56	815	0	0	1
T57	126260	0	0	1
T58	98819	0	0	1
T59	21210	0	0	1
T60	1327	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	477606058	0	0
T1	144372	144287	0	0
T2	12211	12114	0	0
T3	299509	299422	0	0
T4	2554	2497	0	0
T5	358126	358117	0	0
T6	83307	83216	0	0
T7	43632	43546	0	0
T8	103525	103427	0	0
T9	1419	1324	0	0
T10	1064	1014	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477693495	2310226	0	0
T1	144372	832	0	0
T2	12211	1344	0	0
T3	299509	5755	0	0
T4	2554	3	0	0
T5	358126	6981	0	0
T6	83307	832	0	0
T7	43632	1088	0	0
T8	103525	832	0	0
T9	1419	0	0	0
T10	1064	0	0	0
T13	0	832	0	0
T14	0	8174	0	0