Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3174 |
0 |
0 |
T61 |
10289 |
3 |
0 |
0 |
T62 |
8327 |
160 |
0 |
0 |
T63 |
70060 |
4 |
0 |
0 |
T98 |
5433 |
6 |
0 |
0 |
T99 |
15862 |
8 |
0 |
0 |
T101 |
3246 |
124 |
0 |
0 |
T102 |
12917 |
165 |
0 |
0 |
T115 |
29094 |
3 |
0 |
0 |
T116 |
20165 |
4 |
0 |
0 |
T118 |
29003 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1753 |
0 |
0 |
T63 |
70060 |
97 |
0 |
0 |
T99 |
15862 |
23 |
0 |
0 |
T119 |
15050 |
20 |
0 |
0 |
T120 |
4509 |
8 |
0 |
0 |
T121 |
270741 |
663 |
0 |
0 |
T140 |
4818 |
7 |
0 |
0 |
T142 |
5677 |
16 |
0 |
0 |
T146 |
14103 |
67 |
0 |
0 |
T147 |
16893 |
37 |
0 |
0 |
T148 |
9600 |
2 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1830 |
0 |
0 |
T63 |
70060 |
44 |
0 |
0 |
T99 |
15862 |
27 |
0 |
0 |
T119 |
15050 |
34 |
0 |
0 |
T120 |
4509 |
2 |
0 |
0 |
T121 |
270741 |
690 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
18 |
0 |
0 |
T146 |
14103 |
57 |
0 |
0 |
T147 |
16893 |
25 |
0 |
0 |
T148 |
9600 |
5 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
2122 |
0 |
0 |
T63 |
70060 |
102 |
0 |
0 |
T82 |
4574 |
10 |
0 |
0 |
T99 |
15862 |
33 |
0 |
0 |
T119 |
15050 |
27 |
0 |
0 |
T121 |
270741 |
677 |
0 |
0 |
T140 |
4818 |
7 |
0 |
0 |
T142 |
5677 |
14 |
0 |
0 |
T146 |
14103 |
47 |
0 |
0 |
T147 |
16893 |
50 |
0 |
0 |
T149 |
11250 |
24 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5409 |
0 |
0 |
T63 |
70060 |
1183 |
0 |
0 |
T99 |
15862 |
143 |
0 |
0 |
T119 |
15050 |
125 |
0 |
0 |
T120 |
4509 |
7 |
0 |
0 |
T121 |
270741 |
681 |
0 |
0 |
T140 |
4818 |
140 |
0 |
0 |
T142 |
5677 |
6 |
0 |
0 |
T146 |
14103 |
38 |
0 |
0 |
T147 |
16893 |
54 |
0 |
0 |
T148 |
9600 |
67 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
6160 |
0 |
0 |
T63 |
70060 |
1087 |
0 |
0 |
T99 |
15862 |
134 |
0 |
0 |
T119 |
15050 |
396 |
0 |
0 |
T120 |
4509 |
111 |
0 |
0 |
T121 |
270741 |
696 |
0 |
0 |
T140 |
4818 |
139 |
0 |
0 |
T142 |
5677 |
27 |
0 |
0 |
T146 |
14103 |
26 |
0 |
0 |
T147 |
16893 |
22 |
0 |
0 |
T148 |
9600 |
12 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
6461 |
0 |
0 |
T63 |
70060 |
1315 |
0 |
0 |
T99 |
15862 |
115 |
0 |
0 |
T119 |
15050 |
139 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
637 |
0 |
0 |
T142 |
5677 |
47 |
0 |
0 |
T146 |
14103 |
23 |
0 |
0 |
T147 |
16893 |
57 |
0 |
0 |
T148 |
9600 |
40 |
0 |
0 |
T149 |
11250 |
218 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5893 |
0 |
0 |
T63 |
70060 |
1185 |
0 |
0 |
T99 |
15862 |
271 |
0 |
0 |
T119 |
15050 |
253 |
0 |
0 |
T120 |
4509 |
134 |
0 |
0 |
T121 |
270741 |
660 |
0 |
0 |
T140 |
4818 |
9 |
0 |
0 |
T142 |
5677 |
8 |
0 |
0 |
T146 |
14103 |
49 |
0 |
0 |
T147 |
16893 |
12 |
0 |
0 |
T148 |
9600 |
113 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5774 |
0 |
0 |
T63 |
70060 |
1323 |
0 |
0 |
T99 |
15862 |
317 |
0 |
0 |
T119 |
15050 |
284 |
0 |
0 |
T120 |
4509 |
133 |
0 |
0 |
T121 |
270741 |
666 |
0 |
0 |
T140 |
4818 |
129 |
0 |
0 |
T142 |
5677 |
1 |
0 |
0 |
T146 |
14103 |
21 |
0 |
0 |
T147 |
16893 |
47 |
0 |
0 |
T148 |
9600 |
157 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5853 |
0 |
0 |
T63 |
70060 |
959 |
0 |
0 |
T99 |
15862 |
128 |
0 |
0 |
T119 |
15050 |
260 |
0 |
0 |
T120 |
4509 |
142 |
0 |
0 |
T121 |
270741 |
626 |
0 |
0 |
T140 |
4818 |
5 |
0 |
0 |
T142 |
5677 |
34 |
0 |
0 |
T146 |
14103 |
24 |
0 |
0 |
T147 |
16893 |
42 |
0 |
0 |
T148 |
9600 |
70 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5961 |
0 |
0 |
T63 |
70060 |
1403 |
0 |
0 |
T99 |
15862 |
255 |
0 |
0 |
T119 |
15050 |
241 |
0 |
0 |
T120 |
4509 |
132 |
0 |
0 |
T121 |
270741 |
637 |
0 |
0 |
T140 |
4818 |
124 |
0 |
0 |
T142 |
5677 |
32 |
0 |
0 |
T146 |
14103 |
21 |
0 |
0 |
T147 |
16893 |
46 |
0 |
0 |
T148 |
9600 |
54 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
5507 |
0 |
0 |
T63 |
70060 |
1076 |
0 |
0 |
T99 |
15862 |
271 |
0 |
0 |
T119 |
15050 |
273 |
0 |
0 |
T120 |
4509 |
137 |
0 |
0 |
T121 |
270741 |
645 |
0 |
0 |
T140 |
4818 |
124 |
0 |
0 |
T142 |
5677 |
7 |
0 |
0 |
T146 |
14103 |
29 |
0 |
0 |
T147 |
16893 |
13 |
0 |
0 |
T148 |
9600 |
5 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3224 |
0 |
0 |
T63 |
70060 |
361 |
0 |
0 |
T99 |
15862 |
103 |
0 |
0 |
T119 |
15050 |
66 |
0 |
0 |
T120 |
4509 |
43 |
0 |
0 |
T121 |
270741 |
660 |
0 |
0 |
T140 |
4818 |
9 |
0 |
0 |
T142 |
5677 |
18 |
0 |
0 |
T146 |
14103 |
47 |
0 |
0 |
T147 |
16893 |
33 |
0 |
0 |
T148 |
9600 |
31 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3545 |
0 |
0 |
T63 |
70060 |
520 |
0 |
0 |
T99 |
15862 |
113 |
0 |
0 |
T119 |
15050 |
134 |
0 |
0 |
T120 |
4509 |
41 |
0 |
0 |
T121 |
270741 |
723 |
0 |
0 |
T140 |
4818 |
83 |
0 |
0 |
T142 |
5677 |
13 |
0 |
0 |
T146 |
14103 |
43 |
0 |
0 |
T147 |
16893 |
49 |
0 |
0 |
T148 |
9600 |
29 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3496 |
0 |
0 |
T63 |
70060 |
662 |
0 |
0 |
T99 |
15862 |
160 |
0 |
0 |
T119 |
15050 |
58 |
0 |
0 |
T120 |
4509 |
5 |
0 |
0 |
T121 |
270741 |
687 |
0 |
0 |
T140 |
4818 |
7 |
0 |
0 |
T142 |
5677 |
35 |
0 |
0 |
T146 |
14103 |
17 |
0 |
0 |
T147 |
16893 |
36 |
0 |
0 |
T148 |
9600 |
2 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3244 |
0 |
0 |
T63 |
70060 |
466 |
0 |
0 |
T99 |
15862 |
138 |
0 |
0 |
T119 |
15050 |
90 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
676 |
0 |
0 |
T140 |
4818 |
9 |
0 |
0 |
T142 |
5677 |
6 |
0 |
0 |
T146 |
14103 |
35 |
0 |
0 |
T147 |
16893 |
29 |
0 |
0 |
T148 |
9600 |
37 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3354 |
0 |
0 |
T63 |
70060 |
476 |
0 |
0 |
T99 |
15862 |
214 |
0 |
0 |
T119 |
15050 |
120 |
0 |
0 |
T120 |
4509 |
3 |
0 |
0 |
T121 |
270741 |
638 |
0 |
0 |
T140 |
4818 |
8 |
0 |
0 |
T142 |
5677 |
2 |
0 |
0 |
T146 |
14103 |
66 |
0 |
0 |
T147 |
16893 |
15 |
0 |
0 |
T148 |
9600 |
10 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3421 |
0 |
0 |
T63 |
70060 |
675 |
0 |
0 |
T99 |
15862 |
116 |
0 |
0 |
T119 |
15050 |
119 |
0 |
0 |
T120 |
4509 |
45 |
0 |
0 |
T121 |
270741 |
615 |
0 |
0 |
T140 |
4818 |
56 |
0 |
0 |
T142 |
5677 |
36 |
0 |
0 |
T146 |
14103 |
21 |
0 |
0 |
T147 |
16893 |
33 |
0 |
0 |
T148 |
9600 |
17 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3309 |
0 |
0 |
T63 |
70060 |
426 |
0 |
0 |
T99 |
15862 |
191 |
0 |
0 |
T119 |
15050 |
152 |
0 |
0 |
T120 |
4509 |
3 |
0 |
0 |
T121 |
270741 |
646 |
0 |
0 |
T140 |
4818 |
49 |
0 |
0 |
T142 |
5677 |
31 |
0 |
0 |
T146 |
14103 |
58 |
0 |
0 |
T147 |
16893 |
23 |
0 |
0 |
T148 |
9600 |
31 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3086 |
0 |
0 |
T63 |
70060 |
557 |
0 |
0 |
T99 |
15862 |
51 |
0 |
0 |
T119 |
15050 |
12 |
0 |
0 |
T120 |
4509 |
65 |
0 |
0 |
T121 |
270741 |
654 |
0 |
0 |
T140 |
4818 |
26 |
0 |
0 |
T142 |
5677 |
2 |
0 |
0 |
T146 |
14103 |
22 |
0 |
0 |
T147 |
16893 |
18 |
0 |
0 |
T148 |
9600 |
7 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3225 |
0 |
0 |
T63 |
70060 |
450 |
0 |
0 |
T99 |
15862 |
127 |
0 |
0 |
T119 |
15050 |
87 |
0 |
0 |
T120 |
4509 |
39 |
0 |
0 |
T121 |
270741 |
645 |
0 |
0 |
T142 |
5677 |
26 |
0 |
0 |
T146 |
14103 |
34 |
0 |
0 |
T147 |
16893 |
44 |
0 |
0 |
T148 |
9600 |
27 |
0 |
0 |
T149 |
11250 |
52 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3161 |
0 |
0 |
T63 |
70060 |
425 |
0 |
0 |
T99 |
15862 |
146 |
0 |
0 |
T119 |
15050 |
52 |
0 |
0 |
T120 |
4509 |
50 |
0 |
0 |
T121 |
270741 |
679 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
1 |
0 |
0 |
T146 |
14103 |
45 |
0 |
0 |
T147 |
16893 |
40 |
0 |
0 |
T149 |
11250 |
39 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3868 |
0 |
0 |
T63 |
70060 |
847 |
0 |
0 |
T99 |
15862 |
132 |
0 |
0 |
T119 |
15050 |
182 |
0 |
0 |
T120 |
4509 |
41 |
0 |
0 |
T121 |
270741 |
671 |
0 |
0 |
T140 |
4818 |
56 |
0 |
0 |
T142 |
5677 |
22 |
0 |
0 |
T146 |
14103 |
23 |
0 |
0 |
T147 |
16893 |
38 |
0 |
0 |
T148 |
9600 |
14 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3636 |
0 |
0 |
T63 |
70060 |
429 |
0 |
0 |
T99 |
15862 |
109 |
0 |
0 |
T119 |
15050 |
93 |
0 |
0 |
T120 |
4509 |
4 |
0 |
0 |
T121 |
270741 |
685 |
0 |
0 |
T140 |
4818 |
59 |
0 |
0 |
T142 |
5677 |
33 |
0 |
0 |
T146 |
14103 |
67 |
0 |
0 |
T147 |
16893 |
19 |
0 |
0 |
T148 |
9600 |
42 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3419 |
0 |
0 |
T63 |
70060 |
547 |
0 |
0 |
T99 |
15862 |
132 |
0 |
0 |
T119 |
15050 |
71 |
0 |
0 |
T120 |
4509 |
67 |
0 |
0 |
T121 |
270741 |
707 |
0 |
0 |
T140 |
4818 |
5 |
0 |
0 |
T142 |
5677 |
26 |
0 |
0 |
T146 |
14103 |
35 |
0 |
0 |
T147 |
16893 |
38 |
0 |
0 |
T148 |
9600 |
39 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3534 |
0 |
0 |
T63 |
70060 |
510 |
0 |
0 |
T99 |
15862 |
191 |
0 |
0 |
T119 |
15050 |
67 |
0 |
0 |
T120 |
4509 |
64 |
0 |
0 |
T121 |
270741 |
727 |
0 |
0 |
T140 |
4818 |
47 |
0 |
0 |
T142 |
5677 |
12 |
0 |
0 |
T146 |
14103 |
52 |
0 |
0 |
T147 |
16893 |
37 |
0 |
0 |
T148 |
9600 |
74 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3389 |
0 |
0 |
T63 |
70060 |
474 |
0 |
0 |
T99 |
15862 |
163 |
0 |
0 |
T119 |
15050 |
81 |
0 |
0 |
T120 |
4509 |
59 |
0 |
0 |
T121 |
270741 |
658 |
0 |
0 |
T140 |
4818 |
60 |
0 |
0 |
T142 |
5677 |
25 |
0 |
0 |
T146 |
14103 |
36 |
0 |
0 |
T147 |
16893 |
33 |
0 |
0 |
T148 |
9600 |
25 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3319 |
0 |
0 |
T63 |
70060 |
530 |
0 |
0 |
T99 |
15862 |
85 |
0 |
0 |
T119 |
15050 |
65 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
638 |
0 |
0 |
T140 |
4818 |
63 |
0 |
0 |
T142 |
5677 |
21 |
0 |
0 |
T146 |
14103 |
43 |
0 |
0 |
T147 |
16893 |
45 |
0 |
0 |
T148 |
9600 |
11 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3626 |
0 |
0 |
T63 |
70060 |
510 |
0 |
0 |
T99 |
15862 |
142 |
0 |
0 |
T119 |
15050 |
64 |
0 |
0 |
T120 |
4509 |
43 |
0 |
0 |
T121 |
270741 |
634 |
0 |
0 |
T140 |
4818 |
34 |
0 |
0 |
T142 |
5677 |
48 |
0 |
0 |
T146 |
14103 |
11 |
0 |
0 |
T147 |
16893 |
50 |
0 |
0 |
T148 |
9600 |
61 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3057 |
0 |
0 |
T63 |
70060 |
525 |
0 |
0 |
T99 |
15862 |
31 |
0 |
0 |
T119 |
15050 |
21 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
681 |
0 |
0 |
T140 |
4818 |
60 |
0 |
0 |
T142 |
5677 |
32 |
0 |
0 |
T146 |
14103 |
34 |
0 |
0 |
T147 |
16893 |
26 |
0 |
0 |
T148 |
9600 |
22 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3505 |
0 |
0 |
T63 |
70060 |
688 |
0 |
0 |
T99 |
15862 |
135 |
0 |
0 |
T119 |
15050 |
134 |
0 |
0 |
T120 |
4509 |
58 |
0 |
0 |
T121 |
270741 |
650 |
0 |
0 |
T140 |
4818 |
8 |
0 |
0 |
T142 |
5677 |
17 |
0 |
0 |
T146 |
14103 |
28 |
0 |
0 |
T147 |
16893 |
34 |
0 |
0 |
T148 |
9600 |
6 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3528 |
0 |
0 |
T63 |
70060 |
564 |
0 |
0 |
T99 |
15862 |
210 |
0 |
0 |
T119 |
15050 |
115 |
0 |
0 |
T120 |
4509 |
52 |
0 |
0 |
T121 |
270741 |
710 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
20 |
0 |
0 |
T146 |
14103 |
50 |
0 |
0 |
T147 |
16893 |
29 |
0 |
0 |
T148 |
9600 |
38 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3322 |
0 |
0 |
T63 |
70060 |
470 |
0 |
0 |
T99 |
15862 |
58 |
0 |
0 |
T119 |
15050 |
112 |
0 |
0 |
T120 |
4509 |
7 |
0 |
0 |
T121 |
270741 |
721 |
0 |
0 |
T140 |
4818 |
39 |
0 |
0 |
T146 |
14103 |
11 |
0 |
0 |
T147 |
16893 |
24 |
0 |
0 |
T148 |
9600 |
55 |
0 |
0 |
T149 |
11250 |
7 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3434 |
0 |
0 |
T63 |
70060 |
493 |
0 |
0 |
T99 |
15862 |
62 |
0 |
0 |
T119 |
15050 |
75 |
0 |
0 |
T120 |
4509 |
7 |
0 |
0 |
T121 |
270741 |
666 |
0 |
0 |
T140 |
4818 |
51 |
0 |
0 |
T142 |
5677 |
14 |
0 |
0 |
T146 |
14103 |
34 |
0 |
0 |
T147 |
16893 |
18 |
0 |
0 |
T148 |
9600 |
14 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3379 |
0 |
0 |
T63 |
70060 |
587 |
0 |
0 |
T99 |
15862 |
25 |
0 |
0 |
T119 |
15050 |
121 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
639 |
0 |
0 |
T140 |
4818 |
1 |
0 |
0 |
T142 |
5677 |
27 |
0 |
0 |
T146 |
14103 |
24 |
0 |
0 |
T147 |
16893 |
34 |
0 |
0 |
T148 |
9600 |
55 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3140 |
0 |
0 |
T63 |
70060 |
368 |
0 |
0 |
T99 |
15862 |
120 |
0 |
0 |
T119 |
15050 |
60 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
679 |
0 |
0 |
T140 |
4818 |
44 |
0 |
0 |
T142 |
5677 |
11 |
0 |
0 |
T146 |
14103 |
28 |
0 |
0 |
T147 |
16893 |
14 |
0 |
0 |
T148 |
9600 |
8 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1893 |
0 |
0 |
T63 |
70060 |
109 |
0 |
0 |
T99 |
15862 |
30 |
0 |
0 |
T119 |
15050 |
48 |
0 |
0 |
T120 |
4509 |
8 |
0 |
0 |
T121 |
270741 |
595 |
0 |
0 |
T140 |
4818 |
13 |
0 |
0 |
T142 |
5677 |
3 |
0 |
0 |
T146 |
14103 |
72 |
0 |
0 |
T147 |
16893 |
47 |
0 |
0 |
T148 |
9600 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1889 |
0 |
0 |
T63 |
70060 |
126 |
0 |
0 |
T99 |
15862 |
30 |
0 |
0 |
T119 |
15050 |
40 |
0 |
0 |
T120 |
4509 |
14 |
0 |
0 |
T121 |
270741 |
615 |
0 |
0 |
T140 |
4818 |
8 |
0 |
0 |
T142 |
5677 |
9 |
0 |
0 |
T146 |
14103 |
78 |
0 |
0 |
T147 |
16893 |
36 |
0 |
0 |
T148 |
9600 |
10 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1840 |
0 |
0 |
T63 |
70060 |
121 |
0 |
0 |
T99 |
15862 |
27 |
0 |
0 |
T119 |
15050 |
19 |
0 |
0 |
T120 |
4509 |
12 |
0 |
0 |
T121 |
270741 |
638 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
13 |
0 |
0 |
T146 |
14103 |
17 |
0 |
0 |
T147 |
16893 |
23 |
0 |
0 |
T148 |
9600 |
12 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1903 |
0 |
0 |
T63 |
70060 |
107 |
0 |
0 |
T99 |
15862 |
41 |
0 |
0 |
T119 |
15050 |
11 |
0 |
0 |
T120 |
4509 |
8 |
0 |
0 |
T121 |
270741 |
688 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
5 |
0 |
0 |
T146 |
14103 |
85 |
0 |
0 |
T147 |
16893 |
24 |
0 |
0 |
T148 |
9600 |
15 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
2192 |
0 |
0 |
T63 |
70060 |
216 |
0 |
0 |
T99 |
15862 |
29 |
0 |
0 |
T119 |
15050 |
28 |
0 |
0 |
T120 |
4509 |
3 |
0 |
0 |
T121 |
270741 |
696 |
0 |
0 |
T142 |
5677 |
5 |
0 |
0 |
T146 |
14103 |
48 |
0 |
0 |
T147 |
16893 |
35 |
0 |
0 |
T148 |
9600 |
4 |
0 |
0 |
T149 |
11250 |
9 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
3367 |
0 |
0 |
T18 |
278743 |
31 |
0 |
0 |
T19 |
0 |
47 |
0 |
0 |
T35 |
0 |
6 |
0 |
0 |
T48 |
299837 |
0 |
0 |
0 |
T49 |
0 |
19 |
0 |
0 |
T56 |
815 |
0 |
0 |
0 |
T57 |
126260 |
0 |
0 |
0 |
T58 |
98819 |
0 |
0 |
0 |
T59 |
21210 |
0 |
0 |
0 |
T60 |
1327 |
0 |
0 |
0 |
T85 |
411225 |
0 |
0 |
0 |
T97 |
860484 |
0 |
0 |
0 |
T134 |
127208 |
0 |
0 |
0 |
T150 |
0 |
1 |
0 |
0 |
T151 |
0 |
40 |
0 |
0 |
T152 |
0 |
12 |
0 |
0 |
T153 |
0 |
10 |
0 |
0 |
T154 |
0 |
34 |
0 |
0 |
T155 |
0 |
58 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1888 |
0 |
0 |
T63 |
70060 |
82 |
0 |
0 |
T99 |
15862 |
15 |
0 |
0 |
T119 |
15050 |
27 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
673 |
0 |
0 |
T140 |
4818 |
5 |
0 |
0 |
T146 |
14103 |
49 |
0 |
0 |
T147 |
16893 |
73 |
0 |
0 |
T148 |
9600 |
1 |
0 |
0 |
T149 |
11250 |
7 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1877 |
0 |
0 |
T63 |
70060 |
133 |
0 |
0 |
T99 |
15862 |
36 |
0 |
0 |
T119 |
15050 |
27 |
0 |
0 |
T120 |
4509 |
18 |
0 |
0 |
T121 |
270741 |
617 |
0 |
0 |
T140 |
4818 |
8 |
0 |
0 |
T142 |
5677 |
17 |
0 |
0 |
T146 |
14103 |
41 |
0 |
0 |
T147 |
16893 |
52 |
0 |
0 |
T148 |
9600 |
5 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1768 |
0 |
0 |
T63 |
70060 |
71 |
0 |
0 |
T99 |
15862 |
18 |
0 |
0 |
T119 |
15050 |
25 |
0 |
0 |
T120 |
4509 |
7 |
0 |
0 |
T121 |
270741 |
646 |
0 |
0 |
T142 |
5677 |
37 |
0 |
0 |
T146 |
14103 |
19 |
0 |
0 |
T147 |
16893 |
26 |
0 |
0 |
T148 |
9600 |
4 |
0 |
0 |
T149 |
11250 |
4 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1821 |
0 |
0 |
T63 |
70060 |
62 |
0 |
0 |
T99 |
15862 |
26 |
0 |
0 |
T119 |
15050 |
25 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
668 |
0 |
0 |
T140 |
4818 |
3 |
0 |
0 |
T142 |
5677 |
1 |
0 |
0 |
T146 |
14103 |
22 |
0 |
0 |
T147 |
16893 |
29 |
0 |
0 |
T148 |
9600 |
1 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1834 |
0 |
0 |
T63 |
70060 |
76 |
0 |
0 |
T99 |
15862 |
21 |
0 |
0 |
T119 |
15050 |
4 |
0 |
0 |
T120 |
4509 |
4 |
0 |
0 |
T121 |
270741 |
667 |
0 |
0 |
T140 |
4818 |
7 |
0 |
0 |
T142 |
5677 |
6 |
0 |
0 |
T146 |
14103 |
46 |
0 |
0 |
T147 |
16893 |
60 |
0 |
0 |
T148 |
9600 |
13 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1767 |
0 |
0 |
T63 |
70060 |
100 |
0 |
0 |
T99 |
15862 |
32 |
0 |
0 |
T119 |
15050 |
12 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
667 |
0 |
0 |
T140 |
4818 |
4 |
0 |
0 |
T142 |
5677 |
17 |
0 |
0 |
T146 |
14103 |
71 |
0 |
0 |
T147 |
16893 |
12 |
0 |
0 |
T148 |
9600 |
5 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
2355 |
0 |
0 |
T63 |
70060 |
266 |
0 |
0 |
T99 |
15862 |
43 |
0 |
0 |
T119 |
15050 |
54 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
669 |
0 |
0 |
T140 |
4818 |
28 |
0 |
0 |
T142 |
5677 |
14 |
0 |
0 |
T146 |
14103 |
36 |
0 |
0 |
T147 |
16893 |
58 |
0 |
0 |
T148 |
9600 |
22 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1756 |
0 |
0 |
T63 |
70060 |
73 |
0 |
0 |
T82 |
4574 |
6 |
0 |
0 |
T99 |
15862 |
25 |
0 |
0 |
T119 |
15050 |
17 |
0 |
0 |
T121 |
270741 |
700 |
0 |
0 |
T140 |
4818 |
5 |
0 |
0 |
T142 |
5677 |
21 |
0 |
0 |
T146 |
14103 |
36 |
0 |
0 |
T147 |
16893 |
17 |
0 |
0 |
T148 |
9600 |
2 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
2535 |
0 |
0 |
T63 |
70060 |
265 |
0 |
0 |
T99 |
15862 |
58 |
0 |
0 |
T119 |
15050 |
23 |
0 |
0 |
T120 |
4509 |
3 |
0 |
0 |
T121 |
270741 |
780 |
0 |
0 |
T140 |
4818 |
6 |
0 |
0 |
T142 |
5677 |
15 |
0 |
0 |
T146 |
14103 |
32 |
0 |
0 |
T147 |
16893 |
36 |
0 |
0 |
T148 |
9600 |
41 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1931 |
0 |
0 |
T63 |
70060 |
101 |
0 |
0 |
T99 |
15862 |
19 |
0 |
0 |
T119 |
15050 |
17 |
0 |
0 |
T120 |
4509 |
1 |
0 |
0 |
T121 |
270741 |
649 |
0 |
0 |
T140 |
4818 |
15 |
0 |
0 |
T142 |
5677 |
12 |
0 |
0 |
T146 |
14103 |
54 |
0 |
0 |
T147 |
16893 |
54 |
0 |
0 |
T149 |
11250 |
14 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1842 |
0 |
0 |
T63 |
70060 |
114 |
0 |
0 |
T99 |
15862 |
14 |
0 |
0 |
T119 |
15050 |
36 |
0 |
0 |
T120 |
4509 |
8 |
0 |
0 |
T121 |
270741 |
644 |
0 |
0 |
T140 |
4818 |
4 |
0 |
0 |
T142 |
5677 |
15 |
0 |
0 |
T146 |
14103 |
49 |
0 |
0 |
T147 |
16893 |
31 |
0 |
0 |
T148 |
9600 |
3 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1888 |
0 |
0 |
T63 |
70060 |
82 |
0 |
0 |
T99 |
15862 |
30 |
0 |
0 |
T119 |
15050 |
23 |
0 |
0 |
T120 |
4509 |
2 |
0 |
0 |
T121 |
270741 |
659 |
0 |
0 |
T140 |
4818 |
3 |
0 |
0 |
T142 |
5677 |
32 |
0 |
0 |
T146 |
14103 |
41 |
0 |
0 |
T147 |
16893 |
40 |
0 |
0 |
T148 |
9600 |
8 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1718 |
0 |
0 |
T63 |
70060 |
64 |
0 |
0 |
T99 |
15862 |
23 |
0 |
0 |
T119 |
15050 |
21 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
638 |
0 |
0 |
T140 |
4818 |
3 |
0 |
0 |
T142 |
5677 |
16 |
0 |
0 |
T146 |
14103 |
68 |
0 |
0 |
T147 |
16893 |
30 |
0 |
0 |
T148 |
9600 |
5 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1732 |
0 |
0 |
T63 |
70060 |
74 |
0 |
0 |
T99 |
15862 |
19 |
0 |
0 |
T119 |
15050 |
31 |
0 |
0 |
T121 |
270741 |
695 |
0 |
0 |
T140 |
4818 |
1 |
0 |
0 |
T142 |
5677 |
6 |
0 |
0 |
T146 |
14103 |
75 |
0 |
0 |
T147 |
16893 |
26 |
0 |
0 |
T148 |
9600 |
11 |
0 |
0 |
T149 |
11250 |
22 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1813 |
0 |
0 |
T63 |
70060 |
57 |
0 |
0 |
T99 |
15862 |
18 |
0 |
0 |
T119 |
15050 |
24 |
0 |
0 |
T120 |
4509 |
6 |
0 |
0 |
T121 |
270741 |
677 |
0 |
0 |
T140 |
4818 |
3 |
0 |
0 |
T142 |
5677 |
8 |
0 |
0 |
T146 |
14103 |
40 |
0 |
0 |
T147 |
16893 |
15 |
0 |
0 |
T148 |
9600 |
12 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479806074 |
1856 |
0 |
0 |
T63 |
70060 |
100 |
0 |
0 |
T99 |
15862 |
14 |
0 |
0 |
T102 |
12917 |
3 |
0 |
0 |
T119 |
15050 |
24 |
0 |
0 |
T120 |
4509 |
5 |
0 |
0 |
T121 |
270741 |
698 |
0 |
0 |
T142 |
5677 |
15 |
0 |
0 |
T146 |
14103 |
12 |
0 |
0 |
T147 |
16893 |
45 |
0 |
0 |
T148 |
9600 |
14 |
0 |
0 |