Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3603522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4171154

1

T1

5779

T2

881

T3

9252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4324380	1			T1	779		T2	23		T3	4436
values[0x0]	1723381	1			T1	2661		T2	447		T3	4461
values[0x1]	1726915	1			T1	2622		T2	431		T3	4491

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2556796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5217880

1

T1

5856

T2

884

T3

10478

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28805	1			T1	25		T3	54		T4	17
valid_sources[0x01]	31460	1			T1	23		T3	64		T4	20
valid_sources[0x02]	29033	1			T1	26		T2	1		T3	34
valid_sources[0x03]	28210	1			T1	16		T3	49		T4	8
valid_sources[0x04]	28425	1			T1	21		T3	44		T4	10
valid_sources[0x05]	29909	1			T1	27		T3	42		T6	24
valid_sources[0x06]	28591	1			T1	30		T3	52		T4	3
valid_sources[0x07]	31240	1			T1	28		T3	63		T4	8
valid_sources[0x08]	28798	1			T1	27		T3	53		T4	25
valid_sources[0x09]	30431	1			T1	15		T3	53		T4	18
valid_sources[0x0a]	27459	1			T1	32		T3	47		T4	1
valid_sources[0x0b]	27440	1			T1	28		T3	46		T4	25
valid_sources[0x0c]	28876	1			T1	26		T3	43		T6	27
valid_sources[0x0d]	53898	1			T1	18		T3	53		T4	7
valid_sources[0x0e]	28616	1			T1	22		T3	59		T4	8
valid_sources[0x0f]	27149	1			T1	13		T2	2		T3	53
valid_sources[0x10]	29831	1			T1	26		T3	43		T4	5
valid_sources[0x11]	29650	1			T1	27		T2	504		T3	50
valid_sources[0x12]	27591	1			T1	23		T3	60		T4	18
valid_sources[0x13]	30261	1			T1	27		T3	57		T4	16
valid_sources[0x14]	28669	1			T1	19		T3	55		T4	20
valid_sources[0x15]	29854	1			T1	27		T3	54		T4	8
valid_sources[0x16]	35801	1			T1	31		T3	45		T4	10
valid_sources[0x17]	28704	1			T1	28		T3	45		T4	7
valid_sources[0x18]	28953	1			T1	22		T3	52		T4	5
valid_sources[0x19]	29819	1			T1	38		T3	48		T4	1
valid_sources[0x1a]	28288	1			T1	31		T3	45		T4	15
valid_sources[0x1b]	30647	1			T1	27		T3	53		T4	6
valid_sources[0x1c]	27640	1			T1	14		T3	61		T4	11
valid_sources[0x1d]	33586	1			T1	21		T2	1		T3	63
valid_sources[0x1e]	30083	1			T1	17		T3	51		T4	10
valid_sources[0x1f]	27176	1			T1	17		T3	58		T4	12
valid_sources[0x20]	29461	1			T1	25		T3	39		T4	4
valid_sources[0x21]	30642	1			T1	22		T3	60		T4	1
valid_sources[0x22]	29233	1			T1	36		T3	57		T4	8
valid_sources[0x23]	33098	1			T1	21		T3	61		T4	12
valid_sources[0x24]	32228	1			T1	27		T2	1		T3	49
valid_sources[0x25]	28719	1			T1	21		T3	44		T4	8
valid_sources[0x26]	29750	1			T1	24		T2	1		T3	54
valid_sources[0x27]	28223	1			T1	15		T3	43		T4	7
valid_sources[0x28]	29732	1			T1	20		T3	57		T4	5
valid_sources[0x29]	27943	1			T1	20		T3	56		T4	8
valid_sources[0x2a]	30355	1			T1	23		T3	49		T4	8
valid_sources[0x2b]	27317	1			T1	19		T3	59		T4	6
valid_sources[0x2c]	27217	1			T1	25		T3	49		T4	5
valid_sources[0x2d]	28335	1			T1	23		T3	46		T4	4
valid_sources[0x2e]	34252	1			T1	25		T3	51		T4	14
valid_sources[0x2f]	28383	1			T1	23		T3	58		T4	4
valid_sources[0x30]	28231	1			T1	28		T3	41		T4	11
valid_sources[0x31]	30163	1			T1	25		T3	45		T4	6
valid_sources[0x32]	27894	1			T1	30		T3	62		T4	14
valid_sources[0x33]	29800	1			T1	28		T2	1		T3	56
valid_sources[0x34]	30621	1			T1	23		T3	56		T4	1
valid_sources[0x35]	28474	1			T1	18		T3	52		T4	13
valid_sources[0x36]	28111	1			T1	27		T3	44		T4	12
valid_sources[0x37]	28793	1			T1	18		T3	46		T4	17
valid_sources[0x38]	26935	1			T1	28		T3	49		T4	3
valid_sources[0x39]	29596	1			T1	18		T3	60		T4	2
valid_sources[0x3a]	27936	1			T1	17		T3	56		T4	10
valid_sources[0x3b]	27037	1			T1	24		T3	55		T4	18
valid_sources[0x3c]	36669	1			T1	19		T3	48		T4	24
valid_sources[0x3d]	28606	1			T1	26		T2	1		T3	55
valid_sources[0x3e]	28327	1			T1	26		T3	55		T4	13
valid_sources[0x3f]	35504	1			T1	24		T3	69		T4	1
valid_sources[0x40]	31006	1			T1	29		T3	53		T4	25
valid_sources[0x41]	27473	1			T1	20		T3	56		T4	4
valid_sources[0x42]	28900	1			T1	21		T3	40		T4	5
valid_sources[0x43]	29093	1			T1	26		T3	46		T4	2
valid_sources[0x44]	29257	1			T1	24		T2	1		T3	59
valid_sources[0x45]	32694	1			T1	22		T3	50		T4	5
valid_sources[0x46]	28703	1			T1	18		T3	53		T4	3
valid_sources[0x47]	31349	1			T1	21		T3	48		T4	3
valid_sources[0x48]	29957	1			T1	24		T3	61		T4	9
valid_sources[0x49]	29804	1			T1	22		T3	54		T4	6
valid_sources[0x4a]	27755	1			T1	23		T3	51		T4	21
valid_sources[0x4b]	40550	1			T1	29		T3	40		T4	3
valid_sources[0x4c]	38996	1			T1	20		T3	51		T4	12
valid_sources[0x4d]	28675	1			T1	18		T3	46		T4	22
valid_sources[0x4e]	29716	1			T1	22		T3	44		T4	5
valid_sources[0x4f]	30802	1			T1	25		T3	54		T4	10
valid_sources[0x50]	27768	1			T1	19		T3	43		T4	35
valid_sources[0x51]	32572	1			T1	28		T3	68		T4	12
valid_sources[0x52]	35865	1			T1	21		T3	49		T4	12
valid_sources[0x53]	29840	1			T1	23		T3	58		T4	3
valid_sources[0x54]	40894	1			T1	23		T3	48		T4	7
valid_sources[0x55]	28089	1			T1	21		T3	61		T4	15
valid_sources[0x56]	32055	1			T1	25		T3	52		T4	12
valid_sources[0x57]	30364	1			T1	25		T2	379		T3	50
valid_sources[0x58]	28814	1			T1	31		T2	1		T3	48
valid_sources[0x59]	34001	1			T1	20		T3	58		T4	3
valid_sources[0x5a]	30176	1			T1	19		T3	47		T4	4
valid_sources[0x5b]	28840	1			T1	18		T2	1		T3	51
valid_sources[0x5c]	34836	1			T1	27		T3	54		T4	4
valid_sources[0x5d]	29014	1			T1	22		T3	52		T4	13
valid_sources[0x5e]	26911	1			T1	19		T3	53		T6	45
valid_sources[0x5f]	28725	1			T1	28		T3	60		T4	4
valid_sources[0x60]	31012	1			T1	27		T3	56		T4	14
valid_sources[0x61]	27553	1			T1	22		T3	48		T4	33
valid_sources[0x62]	29759	1			T1	24		T3	59		T4	18
valid_sources[0x63]	26719	1			T1	24		T3	36		T4	6
valid_sources[0x64]	34692	1			T1	20		T2	1		T3	49
valid_sources[0x65]	27015	1			T1	19		T3	54		T4	13
valid_sources[0x66]	28348	1			T1	16		T3	45		T4	9
valid_sources[0x67]	36238	1			T1	26		T3	46		T4	17
valid_sources[0x68]	44803	1			T1	26		T3	57		T6	52
valid_sources[0x69]	30742	1			T1	25		T3	57		T4	6
valid_sources[0x6a]	27360	1			T1	30		T3	44		T4	10
valid_sources[0x6b]	27021	1			T1	30		T3	60		T4	9
valid_sources[0x6c]	31960	1			T1	29		T3	47		T4	16
valid_sources[0x6d]	29886	1			T1	25		T3	67		T6	47
valid_sources[0x6e]	29179	1			T1	19		T3	45		T4	22
valid_sources[0x6f]	31000	1			T1	17		T3	65		T4	13
valid_sources[0x70]	28566	1			T1	21		T3	57		T4	3
valid_sources[0x71]	27623	1			T1	31		T3	46		T4	6
valid_sources[0x72]	29422	1			T1	17		T3	63		T4	9
valid_sources[0x73]	26845	1			T1	20		T3	54		T4	5
valid_sources[0x74]	29163	1			T1	28		T3	41		T4	6
valid_sources[0x75]	30217	1			T1	20		T3	49		T4	6
valid_sources[0x76]	29746	1			T1	22		T3	55		T4	6
valid_sources[0x77]	28945	1			T1	27		T3	59		T4	1
valid_sources[0x78]	29864	1			T1	31		T3	62		T4	12
valid_sources[0x79]	30217	1			T1	38		T3	72		T4	25
valid_sources[0x7a]	28663	1			T1	31		T3	46		T6	32
valid_sources[0x7b]	27656	1			T1	23		T3	61		T4	4
valid_sources[0x7c]	29240	1			T1	21		T3	44		T6	46
valid_sources[0x7d]	29738	1			T1	34		T3	53		T4	12
valid_sources[0x7e]	30722	1			T1	23		T2	1		T3	52
valid_sources[0x7f]	28871	1			T1	26		T3	46		T4	3
valid_sources[0x80]	30368	1			T1	32		T3	55		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049919

1

T1

526

T2

8

T3

1183

values[0x0]

all_enables

biggest_size

1571570

1

T1

2654

T2

445

T3

4083

values[0x1]

all_enables

biggest_size

1549665

1

T1

2599

T2

428

T3

3986