Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3625073

1

T1

283

T2

20

T3

4136

full_word

4172223

1

T1

5779

T2

881

T3

9252

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7796776	1			T1	6062		T2	901		T3	13388
auto[TlIntgErrCmd]	165	1			T65	10		T94	12		T95	4
auto[TlIntgErrData]	189	1			T65	12		T94	12		T95	15
auto[TlIntgErrBoth]	166	1			T65	8		T94	6		T95	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4327702

1

T1

779

T2

23

T3

4436

auto[1]

3469594

1

T1

5283

T2

878

T3

8952

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3277314	1			T1	253		T2	15		T3	3253
auto[TlIntgErrNone]	partial	auto[1]	347291	1			T1	30		T2	5		T3	883
auto[TlIntgErrNone]	full_word	auto[0]	1050158	1			T1	526		T2	8		T3	1183
auto[TlIntgErrNone]	full_word	auto[1]	3122013	1			T1	5253		T2	873		T3	8069
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T65	4		T94	3		T95	2
auto[TlIntgErrCmd]	partial	auto[1]	91	1			T65	5		T94	7		T95	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T65	1		T94	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T94	1		T181	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	84	1			T65	5		T94	8		T95	9
auto[TlIntgErrData]	partial	auto[1]	82	1			T65	5		T94	2		T95	5
auto[TlIntgErrData]	full_word	auto[0]	12	1			T65	1		T94	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T65	1		T94	1		T95	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T65	1		T94	3		T95	3
auto[TlIntgErrBoth]	partial	auto[1]	88	1			T65	7		T94	2		T95	8
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T94	1		T183	1		T179	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T181	2		T183	1		T150	1