Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	2798092	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	2798092	0	0
T1	109490	7485	0	0
T2	11316	832	0	0
T3	270382	9148	0	0
T4	64848	1669	0	0
T5	4632	0	0	0
T6	748013	2495	0	0
T7	1919	0	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	1663	0	0
T12	0	1665	0	0
T13	0	15800	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	3017274	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	3017274	0	0
T1	109490	4992	0	0
T2	11316	3804	0	0
T3	270382	5824	0	0
T4	64848	838	0	0
T5	4632	0	0	0
T6	748013	1664	0	0
T7	1919	0	0	0
T8	45258	3759	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	835	0	0
T13	0	9152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	186156	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	186156	0	0
T1	109490	321	0	0
T2	11316	0	0	0
T3	270382	839	0	0
T4	64848	0	0	0
T5	4632	0	0	0
T6	748013	171	0	0
T7	1919	1	0	0
T8	45258	0	0	0
T9	231660	0	0	0
T10	35682	0	0	0
T13	0	944	0	0
T15	0	64	0	0
T23	0	322	0	0
T31	0	33	0	0
T32	0	96	0	0
T33	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	426841	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	426841	0	0
T1	109490	321	0	0
T2	11316	0	0	0
T3	270382	834	0	0
T4	64848	0	0	0
T5	4632	0	0	0
T6	748013	171	0	0
T7	1919	6	0	0
T8	45258	0	0	0
T9	231660	0	0	0
T10	35682	0	0	0
T13	0	944	0	0
T15	0	64	0	0
T23	0	1407	0	0
T31	0	33	0	0
T32	0	96	0	0
T33	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	6220000	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	6220000	0	0
T1	109490	752	0	0
T2	11316	75	0	0
T3	270382	6810	0	0
T4	64848	1518	0	0
T5	4632	29	0	0
T6	748013	7915	0	0
T7	1919	40	0	0
T8	45258	560	0	0
T9	231660	398	0	0
T10	35682	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457483843	13407109	0	0
DepthKnown_A	457483843	457343311	0	0
RvalidKnown_A	457483843	457343311	0	0
WreadyKnown_A	457483843	457343311	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	13407109	0	0
T1	109490	749	0	0
T2	11316	300	0	0
T3	270382	6730	0	0
T4	64848	6551	0	0
T5	4632	129	0	0
T6	748013	7861	0	0
T7	1919	174	0	0
T8	45258	2373	0	0
T9	231660	1815	0	0
T10	35682	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483843	457343311	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0