Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	743873402	598005349	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	743873402	3651510	0	0
GntImpliesValid_A	743873402	3651510	0	0
GrantKnown_A	743873402	598005349	0	0
IdxKnown_A	743873402	598005349	0	0
IndexIsCorrect_A	743873402	3651510	0	0
LockArbDecision_A	743873402	0	0	0
NoReadyValidNoGrant_A	743873402	0	0	0
ReadyAndValidImplyGrant_A	743873402	3651510	0	0
ReqAndReadyImplyGrant_A	743873402	3651510	0	0
ReqImpliesValid_A	743873402	3651510	0	0
ReqStaysHighUntilGranted0_M	743873402	0	0	0
RoundRobin_A	743873402	2	0	956
ValidKnown_A	743873402	598005349	0	0
gen_data_port_assertion.DataFlow_A	743873402	3651510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	598005349	0	0
T1	359498	357348	0	0
T2	11316	11242	0	0
T3	1282258	770102	0	0
T4	85392	75045	0	0
T5	5928	5212	0	0
T6	1114369	930896	0	0
T7	3455	2605	0	0
T8	78990	61791	0	0
T9	323844	276878	0	0
T10	139046	86955	0	0
T11	55040	27520	0	0
T12	55991	55730	0	0
T13	0	932940	0	0
T15	0	177868	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	598005349	0	0
T1	359498	357348	0	0
T2	11316	11242	0	0
T3	1282258	770102	0	0
T4	85392	75045	0	0
T5	5928	5212	0	0
T6	1114369	930896	0	0
T7	3455	2605	0	0
T8	78990	61791	0	0
T9	323844	276878	0	0
T10	139046	86955	0	0
T11	55040	27520	0	0
T12	55991	55730	0	0
T13	0	932940	0	0
T15	0	177868	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	598005349	0	0
T1	359498	357348	0	0
T2	11316	11242	0	0
T3	1282258	770102	0	0
T4	85392	75045	0	0
T5	5928	5212	0	0
T6	1114369	930896	0	0
T7	3455	2605	0	0
T8	78990	61791	0	0
T9	323844	276878	0	0
T10	139046	86955	0	0
T11	55040	27520	0	0
T12	55991	55730	0	0
T13	0	932940	0	0
T15	0	177868	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	2	0	956
T49	256290	1	0	1
T50	0	1	0	0
T51	1081	0	0	1
T52	24725	0	0	1
T53	171984	0	0	1
T54	201126	0	0	1
T55	153417	0	0	1
T56	3303	0	0	1
T57	131819	0	0	1
T58	247674	0	0	1
T59	123758	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	598005349	0	0
T1	359498	357348	0	0
T2	11316	11242	0	0
T3	1282258	770102	0	0
T4	85392	75045	0	0
T5	5928	5212	0	0
T6	1114369	930896	0	0
T7	3455	2605	0	0
T8	78990	61791	0	0
T9	323844	276878	0	0
T10	139046	86955	0	0
T11	55040	27520	0	0
T12	55991	55730	0	0
T13	0	932940	0	0
T15	0	177868	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	743873402	3651510	0	0
T1	359498	8779	0	0
T2	11316	832	0	0
T3	1282258	15753	0	0
T4	85392	832	0	0
T5	5928	0	0	0
T6	1114369	3744	0	0
T7	3455	32	0	0
T8	78990	832	0	0
T9	323844	0	0	0
T10	139046	832	0	0
T11	55040	832	0	0
T12	55991	832	0	0
T13	0	10104	0	0
T15	0	939	0	0
T17	0	4271	0	0
T23	0	1682	0	0
T30	0	4081	0	0
T31	0	139	0	0
T32	0	645	0	0
T33	0	52	0	0
T47	0	13684	0	0
T48	0	65	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T3,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144469888	24655949	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	144469888	635185	0	0
GntImpliesValid_A	144469888	635185	0	0
GrantKnown_A	144469888	24655949	0	0
IdxKnown_A	144469888	24655949	0	0
IndexIsCorrect_A	144469888	635185	0	0
LockArbDecision_A	144469888	0	0	0
NoReadyValidNoGrant_A	144469888	0	0	0
ReadyAndValidImplyGrant_A	144469888	635185	0	0
ReqAndReadyImplyGrant_A	144469888	635185	0	0
ReqImpliesValid_A	144469888	635185	0	0
ReqStaysHighUntilGranted0_M	144469888	0	0	0
RoundRobin_A	144469888	0	0	0
ValidKnown_A	144469888	24655949	0	0
gen_data_port_assertion.DataFlow_A	144469888	635185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	24655949	0	0
T3	505938	167208	0	0
T4	10272	0	0	0
T5	648	648	0	0
T6	183178	6552	0	0
T7	768	768	0	0
T8	16866	0	0	0
T9	46092	45280	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	141512	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	24655949	0	0
T3	505938	167208	0	0
T4	10272	0	0	0
T5	648	648	0	0
T6	183178	6552	0	0
T7	768	768	0	0
T8	16866	0	0	0
T9	46092	45280	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	141512	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	24655949	0	0
T3	505938	167208	0	0
T4	10272	0	0	0
T5	648	648	0	0
T6	183178	6552	0	0
T7	768	768	0	0
T8	16866	0	0	0
T9	46092	45280	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	141512	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	24655949	0	0
T3	505938	167208	0	0
T4	10272	0	0	0
T5	648	648	0	0
T6	183178	6552	0	0
T7	768	768	0	0
T8	16866	0	0	0
T9	46092	45280	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	141512	0	0
T16	0	33864	0	0
T23	0	67848	0	0
T25	0	51584	0	0
T26	0	87200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	635185	0	0
T3	505938	2954	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	257	0	0
T7	768	18	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T12	55991	0	0	0
T13	0	3703	0	0
T17	0	4263	0	0
T23	0	1682	0	0
T30	0	1943	0	0
T33	0	52	0	0
T47	0	6828	0	0
T48	0	65	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144469888	118502301	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	144469888	820898	0	0
GntImpliesValid_A	144469888	820898	0	0
GrantKnown_A	144469888	118502301	0	0
IdxKnown_A	144469888	118502301	0	0
IndexIsCorrect_A	144469888	820898	0	0
LockArbDecision_A	144469888	0	0	0
NoReadyValidNoGrant_A	144469888	0	0	0
ReadyAndValidImplyGrant_A	144469888	820898	0	0
ReqAndReadyImplyGrant_A	144469888	820898	0	0
ReqImpliesValid_A	144469888	820898	0	0
ReqStaysHighUntilGranted0_M	144469888	0	0	0
RoundRobin_A	144469888	0	0	0
ValidKnown_A	144469888	118502301	0	0
gen_data_port_assertion.DataFlow_A	144469888	820898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	118502301	0	0
T1	250008	247942	0	0
T3	505938	332696	0	0
T4	10272	10272	0	0
T5	648	0	0	0
T6	183178	176571	0	0
T7	768	0	0	0
T8	16866	16608	0	0
T9	46092	0	0	0
T10	51682	51346	0	0
T11	27520	27520	0	0
T12	0	55730	0	0
T13	0	791428	0	0
T15	0	177868	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	118502301	0	0
T1	250008	247942	0	0
T3	505938	332696	0	0
T4	10272	10272	0	0
T5	648	0	0	0
T6	183178	176571	0	0
T7	768	0	0	0
T8	16866	16608	0	0
T9	46092	0	0	0
T10	51682	51346	0	0
T11	27520	27520	0	0
T12	0	55730	0	0
T13	0	791428	0	0
T15	0	177868	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	118502301	0	0
T1	250008	247942	0	0
T3	505938	332696	0	0
T4	10272	10272	0	0
T5	648	0	0	0
T6	183178	176571	0	0
T7	768	0	0	0
T8	16866	16608	0	0
T9	46092	0	0	0
T10	51682	51346	0	0
T11	27520	27520	0	0
T12	0	55730	0	0
T13	0	791428	0	0
T15	0	177868	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	118502301	0	0
T1	250008	247942	0	0
T3	505938	332696	0	0
T4	10272	10272	0	0
T5	648	0	0	0
T6	183178	176571	0	0
T7	768	0	0	0
T8	16866	16608	0	0
T9	46092	0	0	0
T10	51682	51346	0	0
T11	27520	27520	0	0
T12	0	55730	0	0
T13	0	791428	0	0
T15	0	177868	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144469888	820898	0	0
T1	250008	3454	0	0
T3	505938	5453	0	0
T4	10272	0	0	0
T5	648	0	0	0
T6	183178	1560	0	0
T7	768	0	0	0
T8	16866	0	0	0
T9	46092	0	0	0
T10	51682	0	0	0
T11	27520	0	0	0
T13	0	6401	0	0
T15	0	939	0	0
T17	0	8	0	0
T30	0	2138	0	0
T31	0	139	0	0
T32	0	645	0	0
T47	0	6856	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	454933626	454847099	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	454933626	2195427	0	0
GntImpliesValid_A	454933626	2195427	0	0
GrantKnown_A	454933626	454847099	0	0
IdxKnown_A	454933626	454847099	0	0
IndexIsCorrect_A	454933626	2195427	0	0
LockArbDecision_A	454933626	0	0	0
NoReadyValidNoGrant_A	454933626	0	0	0
ReadyAndValidImplyGrant_A	454933626	2195427	0	0
ReqAndReadyImplyGrant_A	454933626	2195427	0	0
ReqImpliesValid_A	454933626	2195427	0	0
ReqStaysHighUntilGranted0_M	454933626	0	0	0
RoundRobin_A	454933626	2	0	956
ValidKnown_A	454933626	454847099	0	0
gen_data_port_assertion.DataFlow_A	454933626	2195427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	454847099	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	454847099	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	454847099	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2	0	956
T49	256290	1	0	1
T50	0	1	0	0
T51	1081	0	0	1
T52	24725	0	0	1
T53	171984	0	0	1
T54	201126	0	0	1
T55	153417	0	0	1
T56	3303	0	0	1
T57	131819	0	0	1
T58	247674	0	0	1
T59	123758	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	454847099	0	0
T1	109490	109406	0	0
T2	11316	11242	0	0
T3	270382	270198	0	0
T4	64848	64773	0	0
T5	4632	4564	0	0
T6	748013	747773	0	0
T7	1919	1837	0	0
T8	45258	45183	0	0
T9	231660	231598	0	0
T10	35682	35609	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454933626	2195427	0	0
T1	109490	5325	0	0
T2	11316	832	0	0
T3	270382	7346	0	0
T4	64848	832	0	0
T5	4632	0	0	0
T6	748013	1927	0	0
T7	1919	14	0	0
T8	45258	832	0	0
T9	231660	0	0	0
T10	35682	832	0	0
T11	0	832	0	0
T12	0	832	0	0