Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3032583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3928725

1

T1

930

T2

41

T3

2282

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3781002	1			T1	114		T2	1867		T3	2838
values[0x0]	1589045	1			T1	415		T2	16		T3	464
values[0x1]	1591261	1			T1	466		T2	20		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2170216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4791092

1

T1

941

T2

645

T3

2584

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28186	1			T1	3		T2	14		T3	10
valid_sources[0x01]	23871	1			T2	10		T3	23		T5	1
valid_sources[0x02]	24186	1			T1	1		T2	4		T3	15
valid_sources[0x03]	25474	1			T1	10		T2	16		T3	17
valid_sources[0x04]	24611	1			T1	3		T2	11		T3	13
valid_sources[0x05]	23859	1			T1	7		T2	15		T3	12
valid_sources[0x06]	28486	1			T1	1		T2	1		T3	8
valid_sources[0x07]	26155	1			T1	3		T2	24		T3	12
valid_sources[0x08]	30544	1			T2	9		T3	10		T5	913
valid_sources[0x09]	23974	1			T1	6		T2	7		T3	21
valid_sources[0x0a]	27400	1			T1	7		T2	24		T3	17
valid_sources[0x0b]	30177	1			T1	2		T2	28		T3	17
valid_sources[0x0c]	24474	1			T1	8		T2	17		T3	15
valid_sources[0x0d]	25427	1			T1	3		T2	1		T3	17
valid_sources[0x0e]	26993	1			T1	11		T2	10		T3	20
valid_sources[0x0f]	27717	1			T2	2		T3	16		T6	9
valid_sources[0x10]	26734	1			T1	2		T2	6		T3	17
valid_sources[0x11]	27912	1			T1	2		T2	2		T3	20
valid_sources[0x12]	24467	1			T1	5		T2	3		T3	18
valid_sources[0x13]	24865	1			T2	2		T3	12		T6	4
valid_sources[0x14]	28823	1			T2	5		T3	18		T6	6
valid_sources[0x15]	27776	1			T1	3		T2	9		T3	15
valid_sources[0x16]	24555	1			T2	6		T3	17		T6	4
valid_sources[0x17]	40092	1			T1	4		T2	12		T3	13
valid_sources[0x18]	27943	1			T1	5		T2	5		T3	13
valid_sources[0x19]	29706	1			T1	5		T2	4		T3	21
valid_sources[0x1a]	25369	1			T1	3		T2	17		T3	15
valid_sources[0x1b]	24696	1			T1	2		T2	9		T3	15
valid_sources[0x1c]	34622	1			T1	1		T2	1		T3	15
valid_sources[0x1d]	32371	1			T1	3		T2	1		T3	17
valid_sources[0x1e]	26405	1			T1	3		T2	3		T3	16
valid_sources[0x1f]	24333	1			T1	3		T2	12		T3	10
valid_sources[0x20]	24797	1			T1	2		T2	13		T3	11
valid_sources[0x21]	31911	1			T2	9		T3	17		T5	1
valid_sources[0x22]	31925	1			T1	1		T2	17		T3	14
valid_sources[0x23]	24557	1			T1	9		T2	9		T3	13
valid_sources[0x24]	26359	1			T1	4		T2	5		T3	17
valid_sources[0x25]	23615	1			T1	4		T2	8		T3	18
valid_sources[0x26]	29073	1			T1	4		T2	2		T3	17
valid_sources[0x27]	42556	1			T2	7		T3	13		T6	8
valid_sources[0x28]	32412	1			T1	14		T2	7		T3	8
valid_sources[0x29]	28021	1			T2	6		T3	20		T6	6
valid_sources[0x2a]	25707	1			T1	2		T2	10		T3	20
valid_sources[0x2b]	26175	1			T1	1		T2	7		T3	9
valid_sources[0x2c]	24282	1			T1	3		T2	4		T3	23
valid_sources[0x2d]	23971	1			T1	3		T2	2		T3	25
valid_sources[0x2e]	25848	1			T1	1		T2	14		T3	15
valid_sources[0x2f]	27635	1			T1	9		T2	2		T3	8
valid_sources[0x30]	25654	1			T1	1		T2	14		T3	16
valid_sources[0x31]	26284	1			T1	3		T2	3		T3	16
valid_sources[0x32]	25632	1			T1	7		T2	8		T3	14
valid_sources[0x33]	26925	1			T1	19		T2	7		T3	15
valid_sources[0x34]	23308	1			T1	3		T2	4		T3	16
valid_sources[0x35]	27736	1			T1	1		T2	16		T3	8
valid_sources[0x36]	24667	1			T1	4		T3	16		T6	14
valid_sources[0x37]	25178	1			T1	8		T2	13		T3	13
valid_sources[0x38]	26686	1			T1	2		T2	8		T3	11
valid_sources[0x39]	33002	1			T1	7		T2	7		T3	12
valid_sources[0x3a]	25431	1			T1	5		T2	18		T3	12
valid_sources[0x3b]	27736	1			T1	6		T2	1		T3	16
valid_sources[0x3c]	27302	1			T1	1		T2	4		T3	23
valid_sources[0x3d]	25288	1			T1	2		T2	17		T3	16
valid_sources[0x3e]	24814	1			T2	15		T3	17		T6	5
valid_sources[0x3f]	26787	1			T1	6		T2	1		T3	10
valid_sources[0x40]	32181	1			T1	6		T2	7		T3	17
valid_sources[0x41]	28647	1			T1	8		T2	10		T3	19
valid_sources[0x42]	32735	1			T1	3		T3	12		T6	5
valid_sources[0x43]	24345	1			T2	2		T3	23		T5	1
valid_sources[0x44]	23725	1			T1	4		T2	26		T3	18
valid_sources[0x45]	24727	1			T1	8		T2	2		T3	19
valid_sources[0x46]	25054	1			T2	6		T3	13		T6	5
valid_sources[0x47]	25946	1			T1	3		T2	11		T3	15
valid_sources[0x48]	26621	1			T1	1		T3	10		T6	6
valid_sources[0x49]	26850	1			T1	12		T3	14		T6	2
valid_sources[0x4a]	29819	1			T1	4		T2	1		T3	8
valid_sources[0x4b]	32034	1			T1	2		T2	9		T3	11
valid_sources[0x4c]	23222	1			T2	4		T3	19		T6	10
valid_sources[0x4d]	26781	1			T2	6		T3	17		T6	6
valid_sources[0x4e]	29305	1			T1	5		T2	5		T3	12
valid_sources[0x4f]	25467	1			T1	1		T2	13		T3	14
valid_sources[0x50]	26109	1			T1	3		T2	10		T3	13
valid_sources[0x51]	27223	1			T1	4		T2	8		T3	19
valid_sources[0x52]	33605	1			T1	5		T2	1		T3	18
valid_sources[0x53]	27540	1			T1	11		T2	4		T3	13
valid_sources[0x54]	26492	1			T1	4		T2	3		T3	14
valid_sources[0x55]	28631	1			T1	2		T2	6		T3	19
valid_sources[0x56]	25717	1			T2	1		T3	21		T7	8
valid_sources[0x57]	25525	1			T2	4		T3	19		T6	5
valid_sources[0x58]	26051	1			T2	4		T3	15		T6	17
valid_sources[0x59]	26164	1			T1	3		T2	6		T3	10
valid_sources[0x5a]	27897	1			T1	3		T2	4		T3	13
valid_sources[0x5b]	28465	1			T1	3		T2	5		T3	15
valid_sources[0x5c]	25026	1			T1	1		T2	20		T3	11
valid_sources[0x5d]	24998	1			T1	6		T2	8		T3	13
valid_sources[0x5e]	26430	1			T1	10		T2	8		T3	16
valid_sources[0x5f]	29065	1			T1	5		T2	17		T3	15
valid_sources[0x60]	26366	1			T1	4		T2	3		T3	15
valid_sources[0x61]	24584	1			T1	2		T2	1		T3	19
valid_sources[0x62]	26490	1			T1	1		T3	14		T6	12
valid_sources[0x63]	23468	1			T1	4		T2	15		T3	15
valid_sources[0x64]	25439	1			T1	9		T2	3		T3	17
valid_sources[0x65]	24872	1			T1	8		T2	11		T3	21
valid_sources[0x66]	31748	1			T1	1		T3	21		T6	13
valid_sources[0x67]	30876	1			T2	4		T3	23		T6	5
valid_sources[0x68]	24750	1			T1	8		T2	5		T3	9
valid_sources[0x69]	25596	1			T1	12		T2	6		T3	13
valid_sources[0x6a]	26386	1			T1	4		T2	10		T3	21
valid_sources[0x6b]	26076	1			T1	2		T2	9		T3	12
valid_sources[0x6c]	27501	1			T1	12		T2	5		T3	13
valid_sources[0x6d]	27032	1			T1	3		T2	6		T3	17
valid_sources[0x6e]	24307	1			T1	3		T2	4		T3	18
valid_sources[0x6f]	27372	1			T2	6		T3	14		T6	7
valid_sources[0x70]	24044	1			T1	1		T2	7		T3	17
valid_sources[0x71]	33514	1			T1	2		T2	12		T3	15
valid_sources[0x72]	29227	1			T1	1		T2	3		T3	13
valid_sources[0x73]	27554	1			T1	2		T2	6		T3	8
valid_sources[0x74]	30687	1			T1	19		T2	4		T3	20
valid_sources[0x75]	25864	1			T1	15		T2	3		T3	15
valid_sources[0x76]	27873	1			T1	2		T2	9		T3	18
valid_sources[0x77]	29017	1			T1	3		T2	16		T3	20
valid_sources[0x78]	23912	1			T1	5		T2	5		T3	7
valid_sources[0x79]	22476	1			T1	10		T2	1		T3	17
valid_sources[0x7a]	27512	1			T1	1		T2	4		T3	18
valid_sources[0x7b]	25288	1			T1	8		T2	17		T3	9
valid_sources[0x7c]	23755	1			T1	7		T2	3		T3	12
valid_sources[0x7d]	30066	1			T1	2		T3	7		T6	3
valid_sources[0x7e]	26826	1			T2	7		T3	14		T5	1
valid_sources[0x7f]	31591	1			T1	2		T2	9		T3	27
valid_sources[0x80]	25784	1			T1	6		T2	14		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027172

1

T1

51

T2

27

T3

1392

values[0x0]

all_enables

biggest_size

1461618

1

T1

414

T2

5

T3

464

values[0x1]

all_enables

biggest_size

1439935

1

T1

465

T2

9

T3

426