Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3054625

1

T1

65

T2

1862

T3

1452

full_word

3929955

1

T1

930

T2

41

T3

2282

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6984220	1			T1	995		T2	1903		T3	3734
auto[TlIntgErrCmd]	122	1			T57	8		T58	10		T85	6
auto[TlIntgErrData]	120	1			T57	11		T58	9		T85	7
auto[TlIntgErrBoth]	118	1			T57	11		T58	11		T85	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3784636

1

T1

114

T2

1867

T3

2838

auto[1]

3199944

1

T1

881

T2

36

T3

896

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2757034	1			T1	63		T2	1840		T3	1446
auto[TlIntgErrNone]	partial	auto[1]	297265	1			T1	2		T2	22		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	1027442	1			T1	51		T2	27		T3	1392
auto[TlIntgErrNone]	full_word	auto[1]	2902479	1			T1	879		T2	14		T3	890
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T57	5		T58	4		T85	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T57	3		T58	4		T85	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T58	1		T247	1		T248	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T58	1		T98	1		T249	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T57	4		T58	5		T85	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T57	5		T58	3		T85	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	1		T58	1		T85	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T57	1		T246	1		T250	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T57	4		T58	4		T85	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T57	5		T58	5		T85	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T58	2		T98	1		T246	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T57	2		T245	2		T251	2