Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	565692066	3177547	0	0
gen_wmask[1].MaskCheckPortA_A	565692066	3177547	0	0
gen_wmask[2].MaskCheckPortA_A	565692066	3177547	0	0
gen_wmask[3].MaskCheckPortA_A	565692066	3177547	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565692066	3177547	0	0
T1	5967	832	0	0
T2	7794	87	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	128378	2883	0	0
T6	60259	832	0	0
T7	110660	832	0	0
T8	699983	832	0	0
T9	24551	832	0	0
T10	710777	3741	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565692066	3177547	0	0
T1	5967	832	0	0
T2	7794	87	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	128378	2883	0	0
T6	60259	832	0	0
T7	110660	832	0	0
T8	699983	832	0	0
T9	24551	832	0	0
T10	710777	3741	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565692066	3177547	0	0
T1	5967	832	0	0
T2	7794	87	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	128378	2883	0	0
T6	60259	832	0	0
T7	110660	832	0	0
T8	699983	832	0	0
T9	24551	832	0	0
T10	710777	3741	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565692066	3177547	0	0
T1	5967	832	0	0
T2	7794	87	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	128378	2883	0	0
T6	60259	832	0	0
T7	110660	832	0	0
T8	699983	832	0	0
T9	24551	832	0	0
T10	710777	3741	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	424438300	2001160	0	0
gen_wmask[1].MaskCheckPortA_A	424438300	2001160	0	0
gen_wmask[2].MaskCheckPortA_A	424438300	2001160	0	0
gen_wmask[3].MaskCheckPortA_A	424438300	2001160	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2001160	0	0
T1	5967	832	0	0
T2	6318	5	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2496	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	1819	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2001160	0	0
T1	5967	832	0	0
T2	6318	5	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2496	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	1819	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2001160	0	0
T1	5967	832	0	0
T2	6318	5	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2496	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	1819	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2001160	0	0
T1	5967	832	0	0
T2	6318	5	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2496	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	1819	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	141253766	1176387	0	0
gen_wmask[1].MaskCheckPortA_A	141253766	1176387	0	0
gen_wmask[2].MaskCheckPortA_A	141253766	1176387	0	0
gen_wmask[3].MaskCheckPortA_A	141253766	1176387	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	1176387	0	0
T2	1476	82	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	1922	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	1176387	0	0
T2	1476	82	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	1922	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	1176387	0	0
T2	1476	82	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	1922	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	1176387	0	0
T2	1476	82	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	1922	0	0
T12	0	3551	0	0
T13	0	16606	0	0
T23	0	2594	0	0
T24	0	1026	0	0
T27	0	11041	0	0
T30	72040	0	0	0
T31	0	9360	0	0
T37	0	1579	0	0