Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	2758270	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	2758270	0	0
T1	5967	1663	0	0
T2	6318	0	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	3333	0	0
T6	17795	832	0	0
T7	29930	1663	0	0
T8	600443	1663	0	0
T9	22878	832	0	0
T10	611398	1663	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	3076538	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	3076538	0	0
T1	5967	832	0	0
T2	6318	0	0	0
T3	94514	3697	0	0
T4	94896	832	0	0
T5	50944	8309	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	3703	0	0
T10	611398	832	0	0
T11	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	176685	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	176685	0	0
T2	6318	22	0	0
T3	94514	0	0	0
T4	94896	0	0	0
T5	50944	96	0	0
T6	17795	0	0	0
T7	29930	0	0	0
T8	600443	0	0	0
T9	22878	0	0	0
T10	611398	494	0	0
T12	0	923	0	0
T13	0	3220	0	0
T23	0	666	0	0
T24	0	128	0	0
T27	0	1829	0	0
T30	508475	0	0	0
T31	0	726	0	0
T37	0	323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	386126	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	386126	0	0
T2	6318	22	0	0
T3	94514	0	0	0
T4	94896	0	0	0
T5	50944	419	0	0
T6	17795	0	0	0
T7	29930	0	0	0
T8	600443	0	0	0
T9	22878	0	0	0
T10	611398	494	0	0
T12	0	4191	0	0
T13	0	14451	0	0
T23	0	666	0	0
T24	0	541	0	0
T27	0	1828	0	0
T30	508475	0	0	0
T31	0	726	0	0
T37	0	1385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	5317679	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	5317679	0	0
T1	5967	164	0	0
T2	6318	1881	0	0
T3	94514	2902	0	0
T4	94896	2473	0	0
T5	50944	290	0	0
T6	17795	1007	0	0
T7	29930	62	0	0
T8	600443	23746	0	0
T9	22878	53	0	0
T10	611398	10825	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	426961126	10405008	0	0
DepthKnown_A	426961126	426829860	0	0
RvalidKnown_A	426961126	426829860	0	0
WreadyKnown_A	426961126	426829860	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	10405008	0	0
T1	5967	699	0	0
T2	6318	1881	0	0
T3	94514	12771	0	0
T4	94896	2473	0	0
T5	50944	1291	0	0
T6	17795	1006	0	0
T7	29930	62	0	0
T8	600443	73220	0	0
T9	22878	222	0	0
T10	611398	10791	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426961126	426829860	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0