Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T31
1	0	Covered	T2,T10,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T30
1	0	Unreachable
1	1	Covered	T2,T10,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T31

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T31
1	0	Covered	T5,T10,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T5,T10,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	706945832	564272469	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	706945832	3543339	0	0
GntImpliesValid_A	706945832	3543339	0	0
GrantKnown_A	706945832	564272469	0	0
IdxKnown_A	706945832	564272469	0	0
IndexIsCorrect_A	706945832	3543339	0	0
LockArbDecision_A	706945832	0	0	0
NoReadyValidNoGrant_A	706945832	0	0	0
ReadyAndValidImplyGrant_A	706945832	3543339	0	0
ReqAndReadyImplyGrant_A	706945832	3543339	0	0
ReqImpliesValid_A	706945832	3543339	0	0
ReqStaysHighUntilGranted0_M	706945832	0	0	0
RoundRobin_A	706945832	5	0	956
ValidKnown_A	706945832	564272469	0	0
gen_data_port_assertion.DataFlow_A	706945832	3543339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	564272469	0	0
T1	12143	12078	0	0
T2	9270	7330	0	0
T3	129662	110658	0	0
T4	153168	123937	0	0
T5	205812	128264	0	0
T6	102723	60208	0	0
T7	191390	110570	0	0
T8	799523	699872	0	0
T9	26224	24226	0	0
T10	810156	708234	0	0
T11	0	50176	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	564272469	0	0
T1	12143	12078	0	0
T2	9270	7330	0	0
T3	129662	110658	0	0
T4	153168	123937	0	0
T5	205812	128264	0	0
T6	102723	60208	0	0
T7	191390	110570	0	0
T8	799523	699872	0	0
T9	26224	24226	0	0
T10	810156	708234	0	0
T11	0	50176	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	564272469	0	0
T1	12143	12078	0	0
T2	9270	7330	0	0
T3	129662	110658	0	0
T4	153168	123937	0	0
T5	205812	128264	0	0
T6	102723	60208	0	0
T7	191390	110570	0	0
T8	799523	699872	0	0
T9	26224	24226	0	0
T10	810156	708234	0	0
T11	0	50176	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	5	0	956
T13	228845	1	0	1
T29	115942	0	0	1
T33	694513	0	0	1
T34	487549	0	0	1
T38	203425	0	0	1
T40	29789	0	0	1
T43	964748	0	0	1
T44	113131	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	6846	0	0	1
T55	6760	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	564272469	0	0
T1	12143	12078	0	0
T2	9270	7330	0	0
T3	129662	110658	0	0
T4	153168	123937	0	0
T5	205812	128264	0	0
T6	102723	60208	0	0
T7	191390	110570	0	0
T8	799523	699872	0	0
T9	26224	24226	0	0
T10	810156	708234	0	0
T11	0	50176	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	706945832	3543339	0	0
T1	5967	832	0	0
T2	7794	116	0	0
T3	112088	832	0	0
T4	124032	832	0	0
T5	205812	2982	0	0
T6	102723	832	0	0
T7	191390	832	0	0
T8	799523	832	0	0
T9	26224	832	0	0
T10	810156	5316	0	0
T11	50176	0	0	0
T12	0	4991	0	0
T13	0	20262	0	0
T23	0	3682	0	0
T24	0	1026	0	0
T27	0	13434	0	0
T29	0	634	0	0
T30	144080	0	0	0
T31	445987	9683	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T37	0	1579	0	0
T44	0	336	0	0
T48	46856	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T31
1	0	Covered	T2,T10,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T30
1	0	Unreachable
1	1	Covered	T2,T10,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T10,T31
0	0	1	Unreachable
0	0	0	Covered	T2,T10,T30

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141253766	27329516	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	141253766	591775	0	0
GntImpliesValid_A	141253766	591775	0	0
GrantKnown_A	141253766	27329516	0	0
IdxKnown_A	141253766	27329516	0	0
IndexIsCorrect_A	141253766	591775	0	0
LockArbDecision_A	141253766	0	0	0
NoReadyValidNoGrant_A	141253766	0	0	0
ReadyAndValidImplyGrant_A	141253766	591775	0	0
ReqAndReadyImplyGrant_A	141253766	591775	0	0
ReqImpliesValid_A	141253766	591775	0	0
ReqStaysHighUntilGranted0_M	141253766	0	0	0
RoundRobin_A	141253766	0	0	0
ValidKnown_A	141253766	27329516	0	0
gen_data_port_assertion.DataFlow_A	141253766	591775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	27329516	0	0
T2	1476	1104	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	64640	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	27329516	0	0
T2	1476	1104	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	64640	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	27329516	0	0
T2	1476	1104	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	64640	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	27329516	0	0
T2	1476	1104	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	64640	0	0
T12	0	120016	0	0
T13	0	312256	0	0
T23	0	257400	0	0
T27	0	191296	0	0
T30	72040	70112	0	0
T31	0	23488	0	0
T33	0	72320	0	0
T34	0	56560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	591775	0	0
T2	1476	89	0	0
T3	17574	0	0	0
T4	29136	0	0	0
T5	77434	0	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	2763	0	0
T12	0	4991	0	0
T13	0	12388	0	0
T23	0	3412	0	0
T27	0	6436	0	0
T30	72040	0	0	0
T31	0	1023	0	0
T33	0	2083	0	0
T34	0	1481	0	0
T44	0	336	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T31

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T31
1	0	Covered	T5,T10,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T5,T10,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T31
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141253766	112593433	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	141253766	781728	0	0
GntImpliesValid_A	141253766	781728	0	0
GrantKnown_A	141253766	112593433	0	0
IdxKnown_A	141253766	112593433	0	0
IndexIsCorrect_A	141253766	781728	0	0
LockArbDecision_A	141253766	0	0	0
NoReadyValidNoGrant_A	141253766	0	0	0
ReadyAndValidImplyGrant_A	141253766	781728	0	0
ReqAndReadyImplyGrant_A	141253766	781728	0	0
ReqImpliesValid_A	141253766	781728	0	0
ReqStaysHighUntilGranted0_M	141253766	0	0	0
RoundRobin_A	141253766	0	0	0
ValidKnown_A	141253766	112593433	0	0
gen_data_port_assertion.DataFlow_A	141253766	781728	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	112593433	0	0
T1	6176	6176	0	0
T2	1476	0	0	0
T3	17574	16224	0	0
T4	29136	29136	0	0
T5	77434	77391	0	0
T6	42464	42464	0	0
T7	80730	80730	0	0
T8	99540	99504	0	0
T9	1673	1398	0	0
T10	99379	32286	0	0
T11	0	50176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	112593433	0	0
T1	6176	6176	0	0
T2	1476	0	0	0
T3	17574	16224	0	0
T4	29136	29136	0	0
T5	77434	77391	0	0
T6	42464	42464	0	0
T7	80730	80730	0	0
T8	99540	99504	0	0
T9	1673	1398	0	0
T10	99379	32286	0	0
T11	0	50176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	112593433	0	0
T1	6176	6176	0	0
T2	1476	0	0	0
T3	17574	16224	0	0
T4	29136	29136	0	0
T5	77434	77391	0	0
T6	42464	42464	0	0
T7	80730	80730	0	0
T8	99540	99504	0	0
T9	1673	1398	0	0
T10	99379	32286	0	0
T11	0	50176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	112593433	0	0
T1	6176	6176	0	0
T2	1476	0	0	0
T3	17574	16224	0	0
T4	29136	29136	0	0
T5	77434	77391	0	0
T6	42464	42464	0	0
T7	80730	80730	0	0
T8	99540	99504	0	0
T9	1673	1398	0	0
T10	99379	32286	0	0
T11	0	50176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141253766	781728	0	0
T5	77434	387	0	0
T6	42464	0	0	0
T7	80730	0	0	0
T8	99540	0	0	0
T9	1673	0	0	0
T10	99379	238	0	0
T11	50176	0	0	0
T13	0	7874	0	0
T23	0	270	0	0
T24	0	1026	0	0
T27	0	6998	0	0
T29	0	634	0	0
T30	72040	0	0	0
T31	445987	8660	0	0
T37	0	1579	0	0
T38	0	3844	0	0
T48	46856	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424438300	424349520	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	424438300	2169836	0	0
GntImpliesValid_A	424438300	2169836	0	0
GrantKnown_A	424438300	424349520	0	0
IdxKnown_A	424438300	424349520	0	0
IndexIsCorrect_A	424438300	2169836	0	0
LockArbDecision_A	424438300	0	0	0
NoReadyValidNoGrant_A	424438300	0	0	0
ReadyAndValidImplyGrant_A	424438300	2169836	0	0
ReqAndReadyImplyGrant_A	424438300	2169836	0	0
ReqImpliesValid_A	424438300	2169836	0	0
ReqStaysHighUntilGranted0_M	424438300	0	0	0
RoundRobin_A	424438300	5	0	956
ValidKnown_A	424438300	424349520	0	0
gen_data_port_assertion.DataFlow_A	424438300	2169836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	424349520	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	424349520	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	424349520	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	5	0	956
T13	228845	1	0	1
T29	115942	0	0	1
T33	694513	0	0	1
T34	487549	0	0	1
T38	203425	0	0	1
T40	29789	0	0	1
T43	964748	0	0	1
T44	113131	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	6846	0	0	1
T55	6760	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	424349520	0	0
T1	5967	5902	0	0
T2	6318	6226	0	0
T3	94514	94434	0	0
T4	94896	94801	0	0
T5	50944	50873	0	0
T6	17795	17744	0	0
T7	29930	29840	0	0
T8	600443	600368	0	0
T9	22878	22828	0	0
T10	611398	611308	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424438300	2169836	0	0
T1	5967	832	0	0
T2	6318	27	0	0
T3	94514	832	0	0
T4	94896	832	0	0
T5	50944	2595	0	0
T6	17795	832	0	0
T7	29930	832	0	0
T8	600443	832	0	0
T9	22878	832	0	0
T10	611398	2315	0	0