Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3559 |
0 |
0 |
T57 |
27725 |
2 |
0 |
0 |
T58 |
28670 |
4 |
0 |
0 |
T59 |
4611 |
152 |
0 |
0 |
T83 |
13406 |
3 |
0 |
0 |
T84 |
12411 |
11 |
0 |
0 |
T85 |
68900 |
4 |
0 |
0 |
T86 |
17716 |
233 |
0 |
0 |
T89 |
12534 |
8 |
0 |
0 |
T99 |
5647 |
2 |
0 |
0 |
T100 |
15746 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2861 |
0 |
0 |
T83 |
13406 |
12 |
0 |
0 |
T85 |
68900 |
52 |
0 |
0 |
T99 |
5647 |
2 |
0 |
0 |
T100 |
15746 |
24 |
0 |
0 |
T107 |
77356 |
473 |
0 |
0 |
T108 |
269253 |
749 |
0 |
0 |
T136 |
83161 |
507 |
0 |
0 |
T137 |
9766 |
20 |
0 |
0 |
T138 |
35198 |
101 |
0 |
0 |
T139 |
12885 |
44 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3255 |
0 |
0 |
T83 |
13406 |
27 |
0 |
0 |
T85 |
68900 |
59 |
0 |
0 |
T100 |
15746 |
26 |
0 |
0 |
T107 |
77356 |
518 |
0 |
0 |
T108 |
269253 |
725 |
0 |
0 |
T136 |
83161 |
548 |
0 |
0 |
T137 |
9766 |
21 |
0 |
0 |
T138 |
35198 |
166 |
0 |
0 |
T139 |
12885 |
50 |
0 |
0 |
T140 |
6112 |
2 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3279 |
0 |
0 |
T83 |
13406 |
4 |
0 |
0 |
T85 |
68900 |
170 |
0 |
0 |
T99 |
5647 |
10 |
0 |
0 |
T100 |
15746 |
18 |
0 |
0 |
T107 |
77356 |
488 |
0 |
0 |
T108 |
269253 |
673 |
0 |
0 |
T136 |
83161 |
502 |
0 |
0 |
T137 |
9766 |
41 |
0 |
0 |
T138 |
35198 |
121 |
0 |
0 |
T139 |
12885 |
30 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
7119 |
0 |
0 |
T83 |
13406 |
77 |
0 |
0 |
T85 |
68900 |
1061 |
0 |
0 |
T99 |
5647 |
80 |
0 |
0 |
T100 |
15746 |
95 |
0 |
0 |
T107 |
77356 |
521 |
0 |
0 |
T108 |
269253 |
631 |
0 |
0 |
T136 |
83161 |
557 |
0 |
0 |
T137 |
9766 |
162 |
0 |
0 |
T138 |
35198 |
128 |
0 |
0 |
T139 |
12885 |
64 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
7546 |
0 |
0 |
T83 |
13406 |
88 |
0 |
0 |
T85 |
68900 |
1326 |
0 |
0 |
T99 |
5647 |
9 |
0 |
0 |
T100 |
15746 |
428 |
0 |
0 |
T107 |
77356 |
459 |
0 |
0 |
T108 |
269253 |
597 |
0 |
0 |
T136 |
83161 |
534 |
0 |
0 |
T137 |
9766 |
130 |
0 |
0 |
T138 |
35198 |
120 |
0 |
0 |
T140 |
6112 |
81 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
7585 |
0 |
0 |
T83 |
13406 |
12 |
0 |
0 |
T85 |
68900 |
1266 |
0 |
0 |
T100 |
15746 |
146 |
0 |
0 |
T107 |
77356 |
510 |
0 |
0 |
T108 |
269253 |
715 |
0 |
0 |
T136 |
83161 |
471 |
0 |
0 |
T137 |
9766 |
10 |
0 |
0 |
T138 |
35198 |
151 |
0 |
0 |
T139 |
12885 |
37 |
0 |
0 |
T140 |
6112 |
49 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
7258 |
0 |
0 |
T83 |
13406 |
5 |
0 |
0 |
T85 |
68900 |
1170 |
0 |
0 |
T99 |
5647 |
69 |
0 |
0 |
T100 |
15746 |
40 |
0 |
0 |
T107 |
77356 |
470 |
0 |
0 |
T108 |
269253 |
713 |
0 |
0 |
T136 |
83161 |
556 |
0 |
0 |
T137 |
9766 |
17 |
0 |
0 |
T138 |
35198 |
137 |
0 |
0 |
T140 |
6112 |
86 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
6968 |
0 |
0 |
T83 |
13406 |
162 |
0 |
0 |
T85 |
68900 |
949 |
0 |
0 |
T99 |
5647 |
66 |
0 |
0 |
T100 |
15746 |
252 |
0 |
0 |
T107 |
77356 |
529 |
0 |
0 |
T108 |
269253 |
724 |
0 |
0 |
T136 |
83161 |
558 |
0 |
0 |
T137 |
9766 |
117 |
0 |
0 |
T138 |
35198 |
154 |
0 |
0 |
T140 |
6112 |
56 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
8205 |
0 |
0 |
T83 |
13406 |
103 |
0 |
0 |
T85 |
68900 |
1492 |
0 |
0 |
T99 |
5647 |
72 |
0 |
0 |
T100 |
15746 |
126 |
0 |
0 |
T107 |
77356 |
556 |
0 |
0 |
T108 |
269253 |
682 |
0 |
0 |
T136 |
83161 |
562 |
0 |
0 |
T137 |
9766 |
137 |
0 |
0 |
T138 |
35198 |
176 |
0 |
0 |
T140 |
6112 |
7 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
6924 |
0 |
0 |
T83 |
13406 |
30 |
0 |
0 |
T85 |
68900 |
660 |
0 |
0 |
T99 |
5647 |
71 |
0 |
0 |
T100 |
15746 |
235 |
0 |
0 |
T107 |
77356 |
529 |
0 |
0 |
T108 |
269253 |
680 |
0 |
0 |
T136 |
83161 |
524 |
0 |
0 |
T137 |
9766 |
144 |
0 |
0 |
T138 |
35198 |
115 |
0 |
0 |
T140 |
6112 |
73 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
6896 |
0 |
0 |
T83 |
13406 |
15 |
0 |
0 |
T85 |
68900 |
907 |
0 |
0 |
T99 |
5647 |
52 |
0 |
0 |
T100 |
15746 |
135 |
0 |
0 |
T107 |
77356 |
449 |
0 |
0 |
T108 |
269253 |
762 |
0 |
0 |
T136 |
83161 |
490 |
0 |
0 |
T137 |
9766 |
17 |
0 |
0 |
T138 |
35198 |
110 |
0 |
0 |
T140 |
6112 |
61 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4931 |
0 |
0 |
T83 |
13406 |
70 |
0 |
0 |
T85 |
68900 |
455 |
0 |
0 |
T99 |
5647 |
37 |
0 |
0 |
T100 |
15746 |
119 |
0 |
0 |
T107 |
77356 |
466 |
0 |
0 |
T108 |
269253 |
674 |
0 |
0 |
T136 |
83161 |
506 |
0 |
0 |
T137 |
9766 |
92 |
0 |
0 |
T138 |
35198 |
190 |
0 |
0 |
T140 |
6112 |
19 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4580 |
0 |
0 |
T83 |
13406 |
57 |
0 |
0 |
T85 |
68900 |
653 |
0 |
0 |
T100 |
15746 |
124 |
0 |
0 |
T107 |
77356 |
453 |
0 |
0 |
T108 |
269253 |
685 |
0 |
0 |
T136 |
83161 |
507 |
0 |
0 |
T137 |
9766 |
9 |
0 |
0 |
T138 |
35198 |
117 |
0 |
0 |
T139 |
12885 |
22 |
0 |
0 |
T141 |
10446 |
41 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
5216 |
0 |
0 |
T83 |
13406 |
68 |
0 |
0 |
T85 |
68900 |
588 |
0 |
0 |
T100 |
15746 |
64 |
0 |
0 |
T107 |
77356 |
482 |
0 |
0 |
T108 |
269253 |
697 |
0 |
0 |
T136 |
83161 |
547 |
0 |
0 |
T137 |
9766 |
75 |
0 |
0 |
T138 |
35198 |
193 |
0 |
0 |
T139 |
12885 |
56 |
0 |
0 |
T140 |
6112 |
24 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4955 |
0 |
0 |
T83 |
13406 |
91 |
0 |
0 |
T85 |
68900 |
750 |
0 |
0 |
T99 |
5647 |
9 |
0 |
0 |
T100 |
15746 |
71 |
0 |
0 |
T107 |
77356 |
474 |
0 |
0 |
T108 |
269253 |
695 |
0 |
0 |
T136 |
83161 |
469 |
0 |
0 |
T137 |
9766 |
105 |
0 |
0 |
T138 |
35198 |
200 |
0 |
0 |
T140 |
6112 |
34 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4448 |
0 |
0 |
T83 |
13406 |
3 |
0 |
0 |
T85 |
68900 |
365 |
0 |
0 |
T99 |
5647 |
1 |
0 |
0 |
T100 |
15746 |
67 |
0 |
0 |
T107 |
77356 |
436 |
0 |
0 |
T108 |
269253 |
669 |
0 |
0 |
T136 |
83161 |
554 |
0 |
0 |
T137 |
9766 |
12 |
0 |
0 |
T138 |
35198 |
181 |
0 |
0 |
T140 |
6112 |
4 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4336 |
0 |
0 |
T83 |
13406 |
84 |
0 |
0 |
T85 |
68900 |
592 |
0 |
0 |
T100 |
15746 |
174 |
0 |
0 |
T107 |
77356 |
488 |
0 |
0 |
T108 |
269253 |
627 |
0 |
0 |
T136 |
83161 |
567 |
0 |
0 |
T137 |
9766 |
64 |
0 |
0 |
T138 |
35198 |
107 |
0 |
0 |
T139 |
12885 |
72 |
0 |
0 |
T140 |
6112 |
26 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
5077 |
0 |
0 |
T83 |
13406 |
40 |
0 |
0 |
T85 |
68900 |
578 |
0 |
0 |
T99 |
5647 |
26 |
0 |
0 |
T100 |
15746 |
109 |
0 |
0 |
T107 |
77356 |
485 |
0 |
0 |
T108 |
269253 |
647 |
0 |
0 |
T136 |
83161 |
518 |
0 |
0 |
T137 |
9766 |
47 |
0 |
0 |
T138 |
35198 |
184 |
0 |
0 |
T140 |
6112 |
25 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4755 |
0 |
0 |
T83 |
13406 |
56 |
0 |
0 |
T85 |
68900 |
509 |
0 |
0 |
T91 |
18098 |
1 |
0 |
0 |
T100 |
15746 |
91 |
0 |
0 |
T107 |
77356 |
445 |
0 |
0 |
T108 |
269253 |
727 |
0 |
0 |
T136 |
83161 |
492 |
0 |
0 |
T137 |
9766 |
14 |
0 |
0 |
T138 |
35198 |
170 |
0 |
0 |
T140 |
6112 |
1 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4443 |
0 |
0 |
T83 |
13406 |
77 |
0 |
0 |
T85 |
68900 |
356 |
0 |
0 |
T100 |
15746 |
95 |
0 |
0 |
T107 |
77356 |
463 |
0 |
0 |
T108 |
269253 |
717 |
0 |
0 |
T136 |
83161 |
509 |
0 |
0 |
T137 |
9766 |
67 |
0 |
0 |
T138 |
35198 |
98 |
0 |
0 |
T139 |
12885 |
53 |
0 |
0 |
T140 |
6112 |
28 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4836 |
0 |
0 |
T83 |
13406 |
18 |
0 |
0 |
T85 |
68900 |
577 |
0 |
0 |
T99 |
5647 |
3 |
0 |
0 |
T100 |
15746 |
110 |
0 |
0 |
T107 |
77356 |
557 |
0 |
0 |
T108 |
269253 |
677 |
0 |
0 |
T136 |
83161 |
503 |
0 |
0 |
T137 |
9766 |
14 |
0 |
0 |
T138 |
35198 |
195 |
0 |
0 |
T140 |
6112 |
5 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4708 |
0 |
0 |
T83 |
13406 |
55 |
0 |
0 |
T85 |
68900 |
571 |
0 |
0 |
T99 |
5647 |
42 |
0 |
0 |
T100 |
15746 |
59 |
0 |
0 |
T107 |
77356 |
521 |
0 |
0 |
T108 |
269253 |
630 |
0 |
0 |
T136 |
83161 |
484 |
0 |
0 |
T137 |
9766 |
69 |
0 |
0 |
T138 |
35198 |
144 |
0 |
0 |
T140 |
6112 |
35 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4559 |
0 |
0 |
T83 |
13406 |
62 |
0 |
0 |
T85 |
68900 |
655 |
0 |
0 |
T100 |
15746 |
57 |
0 |
0 |
T107 |
77356 |
435 |
0 |
0 |
T108 |
269253 |
623 |
0 |
0 |
T136 |
83161 |
508 |
0 |
0 |
T137 |
9766 |
19 |
0 |
0 |
T138 |
35198 |
137 |
0 |
0 |
T139 |
12885 |
35 |
0 |
0 |
T140 |
6112 |
1 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4339 |
0 |
0 |
T83 |
13406 |
44 |
0 |
0 |
T85 |
68900 |
570 |
0 |
0 |
T99 |
5647 |
6 |
0 |
0 |
T100 |
15746 |
67 |
0 |
0 |
T107 |
77356 |
449 |
0 |
0 |
T108 |
269253 |
663 |
0 |
0 |
T136 |
83161 |
502 |
0 |
0 |
T137 |
9766 |
21 |
0 |
0 |
T138 |
35198 |
194 |
0 |
0 |
T139 |
12885 |
49 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4584 |
0 |
0 |
T83 |
13406 |
123 |
0 |
0 |
T85 |
68900 |
464 |
0 |
0 |
T99 |
5647 |
4 |
0 |
0 |
T100 |
15746 |
114 |
0 |
0 |
T107 |
77356 |
509 |
0 |
0 |
T108 |
269253 |
680 |
0 |
0 |
T136 |
83161 |
491 |
0 |
0 |
T137 |
9766 |
75 |
0 |
0 |
T138 |
35198 |
144 |
0 |
0 |
T140 |
6112 |
26 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4631 |
0 |
0 |
T83 |
13406 |
69 |
0 |
0 |
T85 |
68900 |
446 |
0 |
0 |
T99 |
5647 |
12 |
0 |
0 |
T100 |
15746 |
57 |
0 |
0 |
T107 |
77356 |
462 |
0 |
0 |
T108 |
269253 |
638 |
0 |
0 |
T136 |
83161 |
516 |
0 |
0 |
T137 |
9766 |
23 |
0 |
0 |
T138 |
35198 |
137 |
0 |
0 |
T139 |
12885 |
46 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4753 |
0 |
0 |
T83 |
13406 |
94 |
0 |
0 |
T85 |
68900 |
655 |
0 |
0 |
T99 |
5647 |
37 |
0 |
0 |
T100 |
15746 |
94 |
0 |
0 |
T107 |
77356 |
466 |
0 |
0 |
T108 |
269253 |
663 |
0 |
0 |
T136 |
83161 |
551 |
0 |
0 |
T137 |
9766 |
64 |
0 |
0 |
T138 |
35198 |
145 |
0 |
0 |
T140 |
6112 |
2 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4779 |
0 |
0 |
T83 |
13406 |
42 |
0 |
0 |
T85 |
68900 |
522 |
0 |
0 |
T99 |
5647 |
41 |
0 |
0 |
T100 |
15746 |
111 |
0 |
0 |
T107 |
77356 |
480 |
0 |
0 |
T108 |
269253 |
684 |
0 |
0 |
T136 |
83161 |
516 |
0 |
0 |
T137 |
9766 |
23 |
0 |
0 |
T138 |
35198 |
151 |
0 |
0 |
T140 |
6112 |
36 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4625 |
0 |
0 |
T83 |
13406 |
11 |
0 |
0 |
T85 |
68900 |
618 |
0 |
0 |
T99 |
5647 |
1 |
0 |
0 |
T100 |
15746 |
51 |
0 |
0 |
T107 |
77356 |
441 |
0 |
0 |
T108 |
269253 |
627 |
0 |
0 |
T136 |
83161 |
515 |
0 |
0 |
T137 |
9766 |
79 |
0 |
0 |
T138 |
35198 |
105 |
0 |
0 |
T140 |
6112 |
27 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4567 |
0 |
0 |
T83 |
13406 |
34 |
0 |
0 |
T85 |
68900 |
365 |
0 |
0 |
T86 |
17716 |
6 |
0 |
0 |
T100 |
15746 |
53 |
0 |
0 |
T107 |
77356 |
552 |
0 |
0 |
T108 |
269253 |
646 |
0 |
0 |
T136 |
83161 |
496 |
0 |
0 |
T137 |
9766 |
77 |
0 |
0 |
T138 |
35198 |
126 |
0 |
0 |
T140 |
6112 |
15 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4258 |
0 |
0 |
T83 |
13406 |
62 |
0 |
0 |
T85 |
68900 |
461 |
0 |
0 |
T99 |
5647 |
34 |
0 |
0 |
T100 |
15746 |
71 |
0 |
0 |
T107 |
77356 |
488 |
0 |
0 |
T108 |
269253 |
717 |
0 |
0 |
T136 |
83161 |
543 |
0 |
0 |
T137 |
9766 |
58 |
0 |
0 |
T138 |
35198 |
207 |
0 |
0 |
T140 |
6112 |
6 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4620 |
0 |
0 |
T83 |
13406 |
73 |
0 |
0 |
T85 |
68900 |
587 |
0 |
0 |
T99 |
5647 |
45 |
0 |
0 |
T100 |
15746 |
19 |
0 |
0 |
T107 |
77356 |
520 |
0 |
0 |
T108 |
269253 |
618 |
0 |
0 |
T136 |
83161 |
551 |
0 |
0 |
T137 |
9766 |
65 |
0 |
0 |
T138 |
35198 |
165 |
0 |
0 |
T140 |
6112 |
1 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
4470 |
0 |
0 |
T83 |
13406 |
30 |
0 |
0 |
T85 |
68900 |
501 |
0 |
0 |
T100 |
15746 |
118 |
0 |
0 |
T107 |
77356 |
529 |
0 |
0 |
T108 |
269253 |
689 |
0 |
0 |
T136 |
83161 |
566 |
0 |
0 |
T137 |
9766 |
57 |
0 |
0 |
T138 |
35198 |
145 |
0 |
0 |
T139 |
12885 |
12 |
0 |
0 |
T140 |
6112 |
6 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3817 |
0 |
0 |
T83 |
13406 |
83 |
0 |
0 |
T85 |
68900 |
311 |
0 |
0 |
T99 |
5647 |
3 |
0 |
0 |
T100 |
15746 |
64 |
0 |
0 |
T107 |
77356 |
441 |
0 |
0 |
T108 |
269253 |
613 |
0 |
0 |
T136 |
83161 |
487 |
0 |
0 |
T137 |
9766 |
60 |
0 |
0 |
T138 |
35198 |
127 |
0 |
0 |
T140 |
6112 |
27 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
5198 |
0 |
0 |
T83 |
13406 |
28 |
0 |
0 |
T85 |
68900 |
490 |
0 |
0 |
T99 |
5647 |
56 |
0 |
0 |
T100 |
15746 |
96 |
0 |
0 |
T107 |
77356 |
501 |
0 |
0 |
T108 |
269253 |
717 |
0 |
0 |
T136 |
83161 |
499 |
0 |
0 |
T137 |
9766 |
53 |
0 |
0 |
T138 |
35198 |
159 |
0 |
0 |
T140 |
6112 |
32 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3098 |
0 |
0 |
T83 |
13406 |
18 |
0 |
0 |
T85 |
68900 |
74 |
0 |
0 |
T99 |
5647 |
6 |
0 |
0 |
T100 |
15746 |
20 |
0 |
0 |
T107 |
77356 |
490 |
0 |
0 |
T108 |
269253 |
662 |
0 |
0 |
T136 |
83161 |
502 |
0 |
0 |
T137 |
9766 |
15 |
0 |
0 |
T138 |
35198 |
132 |
0 |
0 |
T140 |
6112 |
11 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3197 |
0 |
0 |
T83 |
13406 |
17 |
0 |
0 |
T85 |
68900 |
95 |
0 |
0 |
T99 |
5647 |
4 |
0 |
0 |
T100 |
15746 |
30 |
0 |
0 |
T107 |
77356 |
536 |
0 |
0 |
T108 |
269253 |
687 |
0 |
0 |
T136 |
83161 |
498 |
0 |
0 |
T137 |
9766 |
29 |
0 |
0 |
T138 |
35198 |
130 |
0 |
0 |
T140 |
6112 |
12 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3066 |
0 |
0 |
T83 |
13406 |
1 |
0 |
0 |
T85 |
68900 |
106 |
0 |
0 |
T99 |
5647 |
3 |
0 |
0 |
T100 |
15746 |
27 |
0 |
0 |
T107 |
77356 |
493 |
0 |
0 |
T108 |
269253 |
608 |
0 |
0 |
T136 |
83161 |
522 |
0 |
0 |
T137 |
9766 |
25 |
0 |
0 |
T138 |
35198 |
139 |
0 |
0 |
T140 |
6112 |
2 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3381 |
0 |
0 |
T83 |
13406 |
16 |
0 |
0 |
T85 |
68900 |
136 |
0 |
0 |
T99 |
5647 |
2 |
0 |
0 |
T100 |
15746 |
33 |
0 |
0 |
T107 |
77356 |
470 |
0 |
0 |
T108 |
269253 |
691 |
0 |
0 |
T136 |
83161 |
527 |
0 |
0 |
T137 |
9766 |
28 |
0 |
0 |
T138 |
35198 |
170 |
0 |
0 |
T140 |
6112 |
8 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3459 |
0 |
0 |
T83 |
13406 |
17 |
0 |
0 |
T85 |
68900 |
187 |
0 |
0 |
T100 |
15746 |
40 |
0 |
0 |
T107 |
77356 |
484 |
0 |
0 |
T108 |
269253 |
668 |
0 |
0 |
T136 |
83161 |
483 |
0 |
0 |
T137 |
9766 |
21 |
0 |
0 |
T138 |
35198 |
128 |
0 |
0 |
T139 |
12885 |
72 |
0 |
0 |
T140 |
6112 |
16 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
5221 |
0 |
0 |
T12 |
863028 |
39 |
0 |
0 |
T13 |
228845 |
27 |
0 |
0 |
T15 |
0 |
49 |
0 |
0 |
T20 |
0 |
100 |
0 |
0 |
T22 |
1275 |
0 |
0 |
0 |
T23 |
88305 |
0 |
0 |
0 |
T24 |
642615 |
0 |
0 |
0 |
T25 |
908 |
0 |
0 |
0 |
T26 |
1645 |
0 |
0 |
0 |
T27 |
949314 |
0 |
0 |
0 |
T28 |
62686 |
0 |
0 |
0 |
T29 |
115942 |
0 |
0 |
0 |
T118 |
0 |
46 |
0 |
0 |
T142 |
0 |
19 |
0 |
0 |
T143 |
0 |
8 |
0 |
0 |
T144 |
0 |
54 |
0 |
0 |
T145 |
0 |
44 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3076 |
0 |
0 |
T83 |
13406 |
9 |
0 |
0 |
T85 |
68900 |
92 |
0 |
0 |
T100 |
15746 |
32 |
0 |
0 |
T107 |
77356 |
448 |
0 |
0 |
T108 |
269253 |
704 |
0 |
0 |
T136 |
83161 |
543 |
0 |
0 |
T137 |
9766 |
26 |
0 |
0 |
T138 |
35198 |
165 |
0 |
0 |
T139 |
12885 |
46 |
0 |
0 |
T140 |
6112 |
5 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3281 |
0 |
0 |
T83 |
13406 |
26 |
0 |
0 |
T85 |
68900 |
96 |
0 |
0 |
T99 |
5647 |
9 |
0 |
0 |
T100 |
15746 |
37 |
0 |
0 |
T107 |
77356 |
532 |
0 |
0 |
T108 |
269253 |
617 |
0 |
0 |
T136 |
83161 |
516 |
0 |
0 |
T137 |
9766 |
20 |
0 |
0 |
T138 |
35198 |
188 |
0 |
0 |
T140 |
6112 |
4 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2989 |
0 |
0 |
T83 |
13406 |
13 |
0 |
0 |
T85 |
68900 |
73 |
0 |
0 |
T100 |
15746 |
20 |
0 |
0 |
T107 |
77356 |
513 |
0 |
0 |
T108 |
269253 |
616 |
0 |
0 |
T136 |
83161 |
531 |
0 |
0 |
T137 |
9766 |
9 |
0 |
0 |
T138 |
35198 |
133 |
0 |
0 |
T139 |
12885 |
57 |
0 |
0 |
T140 |
6112 |
2 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3154 |
0 |
0 |
T83 |
13406 |
6 |
0 |
0 |
T85 |
68900 |
56 |
0 |
0 |
T99 |
5647 |
1 |
0 |
0 |
T100 |
15746 |
25 |
0 |
0 |
T107 |
77356 |
503 |
0 |
0 |
T108 |
269253 |
656 |
0 |
0 |
T136 |
83161 |
545 |
0 |
0 |
T137 |
9766 |
10 |
0 |
0 |
T138 |
35198 |
145 |
0 |
0 |
T139 |
12885 |
21 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3038 |
0 |
0 |
T83 |
13406 |
4 |
0 |
0 |
T85 |
68900 |
72 |
0 |
0 |
T100 |
15746 |
27 |
0 |
0 |
T107 |
77356 |
482 |
0 |
0 |
T108 |
269253 |
669 |
0 |
0 |
T136 |
83161 |
502 |
0 |
0 |
T137 |
9766 |
14 |
0 |
0 |
T138 |
35198 |
184 |
0 |
0 |
T139 |
12885 |
40 |
0 |
0 |
T140 |
6112 |
6 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3094 |
0 |
0 |
T83 |
13406 |
12 |
0 |
0 |
T85 |
68900 |
76 |
0 |
0 |
T99 |
5647 |
7 |
0 |
0 |
T100 |
15746 |
24 |
0 |
0 |
T107 |
77356 |
508 |
0 |
0 |
T108 |
269253 |
607 |
0 |
0 |
T136 |
83161 |
583 |
0 |
0 |
T137 |
9766 |
26 |
0 |
0 |
T138 |
35198 |
152 |
0 |
0 |
T139 |
12885 |
46 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3537 |
0 |
0 |
T83 |
13406 |
25 |
0 |
0 |
T85 |
68900 |
180 |
0 |
0 |
T100 |
15746 |
38 |
0 |
0 |
T107 |
77356 |
479 |
0 |
0 |
T108 |
269253 |
655 |
0 |
0 |
T136 |
83161 |
550 |
0 |
0 |
T137 |
9766 |
17 |
0 |
0 |
T138 |
35198 |
162 |
0 |
0 |
T139 |
12885 |
12 |
0 |
0 |
T140 |
6112 |
9 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2951 |
0 |
0 |
T83 |
13406 |
20 |
0 |
0 |
T85 |
68900 |
76 |
0 |
0 |
T100 |
15746 |
23 |
0 |
0 |
T107 |
77356 |
426 |
0 |
0 |
T108 |
269253 |
679 |
0 |
0 |
T136 |
83161 |
506 |
0 |
0 |
T137 |
9766 |
11 |
0 |
0 |
T138 |
35198 |
124 |
0 |
0 |
T139 |
12885 |
18 |
0 |
0 |
T140 |
6112 |
3 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3557 |
0 |
0 |
T83 |
13406 |
43 |
0 |
0 |
T85 |
68900 |
178 |
0 |
0 |
T99 |
5647 |
11 |
0 |
0 |
T100 |
15746 |
50 |
0 |
0 |
T107 |
77356 |
516 |
0 |
0 |
T108 |
269253 |
645 |
0 |
0 |
T136 |
83161 |
548 |
0 |
0 |
T137 |
9766 |
13 |
0 |
0 |
T138 |
35198 |
145 |
0 |
0 |
T140 |
6112 |
4 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3142 |
0 |
0 |
T83 |
13406 |
21 |
0 |
0 |
T85 |
68900 |
94 |
0 |
0 |
T99 |
5647 |
4 |
0 |
0 |
T100 |
15746 |
34 |
0 |
0 |
T107 |
77356 |
422 |
0 |
0 |
T108 |
269253 |
746 |
0 |
0 |
T136 |
83161 |
536 |
0 |
0 |
T137 |
9766 |
9 |
0 |
0 |
T138 |
35198 |
162 |
0 |
0 |
T140 |
6112 |
3 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3028 |
0 |
0 |
T83 |
13406 |
25 |
0 |
0 |
T85 |
68900 |
63 |
0 |
0 |
T99 |
5647 |
5 |
0 |
0 |
T100 |
15746 |
31 |
0 |
0 |
T107 |
77356 |
509 |
0 |
0 |
T108 |
269253 |
623 |
0 |
0 |
T136 |
83161 |
540 |
0 |
0 |
T137 |
9766 |
14 |
0 |
0 |
T138 |
35198 |
161 |
0 |
0 |
T139 |
12885 |
37 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3046 |
0 |
0 |
T83 |
13406 |
14 |
0 |
0 |
T85 |
68900 |
68 |
0 |
0 |
T99 |
5647 |
6 |
0 |
0 |
T100 |
15746 |
26 |
0 |
0 |
T107 |
77356 |
522 |
0 |
0 |
T108 |
269253 |
683 |
0 |
0 |
T136 |
83161 |
602 |
0 |
0 |
T137 |
9766 |
15 |
0 |
0 |
T138 |
35198 |
99 |
0 |
0 |
T140 |
6112 |
5 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2785 |
0 |
0 |
T83 |
13406 |
9 |
0 |
0 |
T85 |
68900 |
73 |
0 |
0 |
T99 |
5647 |
9 |
0 |
0 |
T100 |
15746 |
17 |
0 |
0 |
T107 |
77356 |
447 |
0 |
0 |
T108 |
269253 |
668 |
0 |
0 |
T136 |
83161 |
502 |
0 |
0 |
T137 |
9766 |
12 |
0 |
0 |
T138 |
35198 |
139 |
0 |
0 |
T140 |
6112 |
9 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2864 |
0 |
0 |
T83 |
13406 |
24 |
0 |
0 |
T85 |
68900 |
71 |
0 |
0 |
T99 |
5647 |
11 |
0 |
0 |
T100 |
15746 |
20 |
0 |
0 |
T107 |
77356 |
493 |
0 |
0 |
T108 |
269253 |
574 |
0 |
0 |
T136 |
83161 |
532 |
0 |
0 |
T137 |
9766 |
17 |
0 |
0 |
T138 |
35198 |
176 |
0 |
0 |
T140 |
6112 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
2882 |
0 |
0 |
T83 |
13406 |
4 |
0 |
0 |
T85 |
68900 |
54 |
0 |
0 |
T100 |
15746 |
16 |
0 |
0 |
T107 |
77356 |
479 |
0 |
0 |
T108 |
269253 |
587 |
0 |
0 |
T136 |
83161 |
522 |
0 |
0 |
T137 |
9766 |
18 |
0 |
0 |
T138 |
35198 |
120 |
0 |
0 |
T139 |
12885 |
54 |
0 |
0 |
T140 |
6112 |
10 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
426961126 |
3102 |
0 |
0 |
T83 |
13406 |
12 |
0 |
0 |
T85 |
68900 |
68 |
0 |
0 |
T100 |
15746 |
28 |
0 |
0 |
T107 |
77356 |
500 |
0 |
0 |
T108 |
269253 |
647 |
0 |
0 |
T136 |
83161 |
574 |
0 |
0 |
T137 |
9766 |
9 |
0 |
0 |
T138 |
35198 |
149 |
0 |
0 |
T139 |
12885 |
78 |
0 |
0 |
T140 |
6112 |
3 |
0 |
0 |